Unit 1 Part 2

By
Dr. Gourav Verma
Associate Prof.
ECE Dept.
Topics
• Combinational Logic: Introduction, Analysis & Design Procedure,
• Binary Adder & Subtractor,
• Decimal Adder,
• Binary Multiplier,
• Magnitude Comparator,
• Decoders,
• Encoders,
• Multiplexers,
• De- Multiplexers,
• code conversion.
• Introduction to HDL description of combinational logic circuits.
 Magnitude Comparator
• A magnitude comparator is a combinational
circuit that
compares two numbers A & B to determine
whether:
• A > B, or A = B, or A < B
2 bit magnitude comparator
Magnitude Comparator…

𝑌 2=( 𝐴1 ʘ 𝐵 1)+( 𝐴0 ʘ 𝐵 0) Y3
Multiplexers
• Multiplexers come in multiple variations
• 2 : 1 multiplexer
• 4 : 1 multiplexer
• 16 : 1 multiplexer
• 32 : 1 multiplexer
4:1 Mux
Boolean function implementation
• F(x, y, z) = Ʃ(1,2,6,7)

4x1 Mux
F
1

x
I0 I1 I2 I3

𝑥 0 1 2 3
x 4 5 6 7
0 𝑥 1 x
y z
• F(A, B, C, D) = Ʃ(1, 3, 4, 11, 12, 13, 14, 15)

0
𝑥
0

8x1 Mux
1
F
1
x
x
x I0 I1 I2 I3 I4 I5 I6 I7
𝑥 0 1 2 3 4 5 6 7
y z x 8 9 10 11 12 13 14 15
0 𝑥 0 1 1 x x x
Task
• Make all gates using 2x1 Mux
16x1 using 4x1
• Advantages of MUX: Given below are the Advantages of MUX
• Efficiency: The Mux has good efficiency in routing multiple input signals to a single out signal based on control
signals.
• Optimization: The Mux helps to conserve resources such as wires, pins and integrated circuit(IC).
• Different Implementation: The Mux can be used to implement different digital logic functions such AND,OR
etc.
• Flexibility: Mux can be easily configure according to the requirements and accommodate different data
sources, enhancing system versatility.
• Disadvantages of MUX
• Given Below are the Disadvantages of MUX
• Limited number of data sources: The number of input that can be taken by a multiplexer is restricted by the
number of control lines, which can cause limitations in certain applications.
• Delay: Multiplexers can have some delay in the signal path, which can have impact on the performance of the
circuit.
• Complex control rationale: The control logic for multiplexers can be complex, particularly for bigger
multiplexers with an large number of inputs.
• Power utilization: Multiplexers can consume more power compared with other simple logic gate, particularly
when they have a large number of inputs.
• Applications of MUX
• Given Below are the Applications of MUX
• Data Routing: The Mux is used for data routing in the digital system where they select one of the several data
lines and re-route it the output.
• Data Selection: The Mux is used for data selection where they select data source according to the select lines.
• Analog-to-Digital Conversion: The Mux are used in ADC to select different analog input channels.
• Address Decoding: The Mux are used in Microprocessors or memory for address decoding.
Binay Multiplier
BINARY-TO-GRAY
And G3 = B3
Gray-to-Binary

And B3 = G3
Unit 2
Sequential Logic
Unit 2
• Sequential Logic: Introduction, Types of Seguential circuits
• Basic storage elements (Latch and Flip-flops),
• Characteristic equations & tables, excitation table,
• Flip-flop conversion,
• Register, Universal Shift register.
Sequential Logic
Sequential circuits are digital circuits that store and use the previous state
information to determine their next state. Unlike combinational circuits, which
only depend on the current input values to produce outputs, sequential circuits
depend on both the current inputs and the previous state stored in memory
elements.
1.Sequential circuits are commonly used in digital systems to implement state
machines, timers, counters, and memory elements. The memory elements in
sequential circuits can be implemented using flip-flops, which are circuits that
store binary values and maintain their state even when the inputs change.
2.There are two types of sequential circuits: finite state machines (FSMs) and
synchronous sequential circuits. FSMs are designed to have a limited number
of states and are typically used to implement state machines and control
systems. Synchronous sequential circuits, on the other hand, are designed to
have an infinite number of states and are typically used to implement timers,
counters, and memory elements.
As shown in the figure, there are two types of input
to the combinational logic :
1.External inputs which are not controlled by the
circuit.
2.Internal inputs, which are a function of a previous
output state.
Secondary inputs are state variables produced by
the storage elements, whereas secondary outputs
are excitations for the storage elements.
• Types of Sequential Circuits:
• There are two types of sequential circuits:
• Type 1: Asynchronous sequential circuit: These
circuits do not use a clock signal but uses the
pulses of the inputs. These circuits
are faster than synchronous sequential circuits
because there is clock pulse and change their
state immediately when there is a change in the
input signal. We use asynchronous sequential
circuits when speed of operation is important
and independent of internal clock pulse.
• But these circuits are more difficult to design
and their output is uncertain.
• Type2: Synchronous sequential circuit: These
circuits uses clock signal and level inputs
(or pulsed) (with restrictions on pulse width
and circuit propagation). The output pulse is
the same duration as the clock pulse for the
clocked sequential circuits. Since they wait for
the next clock pulse to arrive to perform the
next operation, so these circuits are
bit slower compared to asynchronous. Level
output changes state at the start of an input
pulse and remains in that until the next input
or clock pulse.
• We use synchronous sequential circuit in
synchronous counters, flip flops, and in the
design of MOORE-MEALY state management
machines. We use sequential circuits to
design Counters, Registers, RAM,
MOORE/MEALY Machine and other state
retaining machines.
Advantages of Sequential
Circuits:
• Memory: Sequential circuits have the ability to store binary values,
which makes them ideal for applications that require memory elements,
such as timers and counters.
• Timing: Sequential circuits are commonly used to implement timing and
synchronization in digital systems, making them essential for real-time
control applications.
• State machine implementation: Sequential circuits can be used to
implement state machines, which are useful for controlling complex
digital systems and ensuring that they operate as intended.
• Error detection: Sequential circuits can be designed to detect errors in
digital systems and respond accordingly, improving the reliability of
digital systems.
Disadvantages of Sequential
Circuits:
• Complexity: Sequential circuits are typically more
complex than combinational circuits and require more
components to implement.
• Timing constraints: The design of sequential circuits
can be challenging due to the need to ensure that the
timing of the inputs and outputs is correct.
• Testing and debugging: Testing and debugging
sequential circuits can be more difficult compared to
combinational circuits due to their complex structure
and state-dependant outputs.
Difference between Flip-flop
and Latch
S. NO. Flip-flop Latch
1 Flip-flop is a bistable device i.e., it has two stable states Latch is also a bistable device whose
that are represented as 0 and 1. states are also represented as 0 and 1.

It checks the inputs continuously and

2 It checks the inputs but changes the output only at times responds to the changes in inputs
defined by the clock signal or any other control signal. immediately.
3 It is a edge triggered device. It is a level triggered device.

4 Gates like NOR, NOT, AND, NAND are building blocks of These are also made up of gates.
flip flops.

5 They are classified into asynchronous or synchronous There is no such classification in latches.
flipflops.

These can be used for the designing of

6 It forms the building blocks of many sequential circuits sequential circuits but are not generally
like counters. preferred.
7 a, Flip-flop always have a clock signal Latches doesn’t have a clock signal
8 Flip-flop can be build from Latches Latches can be build from gates
9 ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch
Race-round Condition in JK FF
• If both the J and K inputs are HIGH at logic “1” (J = K = 1), when the clock input
goes HIGH, the circuit will “toggle” as its outputs switch and change state
complementing each other.
• This results in the JK flip-flop acting more like a T-type toggle flip-flop when both
terminals are “HIGH”.
• However, as the outputs are fed back to the inputs, this can cause the output
at Q to oscillate between SET and RESET continuously after being
complemented once.
• While this JK flip-flop circuit is an improvement on the clocked SR flip-flop it also
suffers from timing problems called “race” if the output Q changes state before
the timing pulse of the clock input has time to go “OFF”.
• To avoid this the timing pulse period ( T ) must be kept as short as possible
(high frequency).
• As this is sometimes not possible with basic JK’s built using basic NAND or NOR
gates, far more advanced master-slave (edge-triggered) flip-flops were
developed which are more stabe.
Master-Slave (edge-triggered) flip-
flops
Preset /clear
Characteristic equations & tables: RS LATCH
Characteristic equations & tables: D LATCH

0
1
0
1
Characteristic equations & tables: JK LATCH
Characteristic equations & tables: T LATCH
Excitation Table and Flip -Flop conversion
Conversion of SR FF into D FF
Conversion of SR FF into JK FF

KQ(t)
Conversion of SR FF into T FF
Conversion of D FF into JK FF
Conversion of D FF into JK FF
Shift Registers
SISO Shift Registers
SIPO Shift Registers
PISO Shift Registers
PIPO Shift Registers
Universal Shift Registers
Unit 3
Dr Gaurav Verma
Associate Professor
Dept of ECE
Contents
• Counters: Ripple & Synchronous binary counters,
• BCD counter,
• mod-n counter,
• Ring & Johnson counter.
• Mealy and Moore model.
• Design and analysis of synchronous sequential circuit.
• State diagram and state table.
Counters
• A special type of sequential circuit used to count the
pulse is known as a counter, or a collection of flip flops
where the clock signal is applied is known as counters.
• The counter is one of the widest applications of the flip
flop. Based on the clock pulse, the output of the counter
contains a predefined state.
• The number of the pulse can be counted using the
output of the counter.
 Truth Table

There are the following types of counters:

• Asynchronous Counters
• Synchronous Counters

In the Asynchronous counter, the present counter's output passes to the input of the next counter.
So, the counters are connected like a chain. The drawback of this system is that it creates the
counting delay, and the propagation delay also occurs during the counting stage. The synchronous
counter is designed to remove this drawback.
Asynchronous or ripple counters
Synchronous counters

• In the synchronous counter, the same clock pulse is

passed to the clock input of all the flip flops. The clock
signals produced by all the flip flops are the same as
each other. Below is the diagram of a 2-bit synchronous
counter in which the inputs of the first flip flop, i.e., FF-
A, are set to 1. So, the first flip flop will work as a toggle
flip-flop. The output of the first flip flop is passed to both
the inputs of the next JK flip flop.
4 bit synchronous counter
Decade Counter/BCD Counter
Clock
Q3 Q2 Q1 Q0
pulse

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0
Design Mod – N synchronous
Counter
• Design for Mod-N counter :
• The steps for the design are –

• Step 1 : Decision for number of flip-flops –

Example : If we are designing mod N counter and n number of flip-flops are required then n
can be found out by this equation.

• N <= 2n
• Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops(n)
required is
• For n =3, 10<=8, which is false.
• For n= 4,10<=16, which is true.
• Step 2 : Write excitation table of Flip flops –
Here T FF is used
• Step 3 : Draw state diagram and circuit excitation
table –

A decade counter is called as mod -10 or divide by 10 counter. It counts from 0 to 9

and again reset to 0. It counts in natural binary sequence. Here 4 T Flip flops are used.
It resets after Q3 Q2 Q1 Q0 = 1001.
• Circuit excitation table –
Here Q3 Q2 Q1 Q0 are present states of four flip-flops and
Q*3 Q*2 Q*1 Q*0 are next counting state of 4 Flip flops. If
there is a transition in current state i.e if Q3 value
changes from 0 to 1 or 1 to 0 then there’s
corresponding T(toggle) bit is written as 1 otherwise 0.
Step 4 : Create Karnaugh map for each FF input in
terms of flip-flop outputs as the input variable –
Simplify the K map –
• Step 5 : Create circuit diagram –
Here negative edge triggered clock is used for toggling
purpose.
• The clock is provided to every Flip flop at same instant
of time.
• The toggle(T) input is provided to every Flip flop
according to the simplified equation of K map.
• Explanation :
• Initially Q3 Q2 Q1 Q0 are 0 0 0 0.
• The sequence of counter can be verified from the timing diagram. At every falling
edge of the clock output Q0 toggles because T0 is connected to logic 1.
• T1 becomes 1 only when expression T1 = Q’3Q0 becomes 1 also if clock falling edge
occurs(because there is negative edge triggering) then the output state of T1 i.e
Q1 will change.
• T2 becomes 1 only when expression T2 = Q1Q0 becomes 1 also if clock falling edge
occurs then the output state Q2 will change.
• T3 becomes 1 only when expression T1 = Q3Q0 + Q2Q1Q0 resultant becomes 1 also if
clock falling edge occurs(because there is negative edge triggering) then the state of
Q3 will change.
• We get Output as Q3(MSB) Q2 Q1 Q0(LSB).
• After 10th falling edge the output state of all the FFs again becomes 0 0 0 0.
Mod 3 counter
UP/DOWN Counter
RING Counter
Johnson Counter
Moore Machine
Mealy Machine
Difference between Moore and Mealy Models
 State, State Transition and State Diagram

Mealy M/C Moore M/C

State Table Mealy M/C
Example: Construct the Transition Table, State Table, and State Diagram for the Moore Sequential Logic given
Below