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Lab3 System Functions

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0% found this document useful (0 votes)
6 views

Lab3 System Functions

Uploaded by

Ayan Shaikh
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CLPD LAB-3

• System Functions
Understanding
Verilog System
tasks
• These are tasks and functions that are used to generate input and
output during simulation.

• Their names begin with a dollar sign ($).

• The Synopsys Verilog HDL Compiler/Design Compiler and many other


synthesis tools parse and ignore system functions, and hence can be
included even in synthesizable models.
$display, $monitor,
$strobe

• These commands have the same syntax and display their values as text on the screen
during simulation.

• $display/$strobe-$display and $strobe display once every time they are executed.

• $monitor-$monitor displays every time one of its parameters changes.

• The difference between $display and $strobe is that $strobe displays the parameters at the
very end of the current simulation time unit.
Examp
le 1
With value of a, b changing,
$monitor executes thrice..!
$stro
be

Everytime, $strobe is executed at last of


current simulation time i.e 3 or 0 (though
it is written above $display)
$rando
m:
Forever
Loop :
•The keyword forever in Verilog
creates a block of code that will run
continuously. It is similar to other
loops in Verilog such as for
loops and while loops.

•The main difference between these


and the forever loop is that the
forever loop will never stop running,
whereas for and while have a limit.

•Forever Loops should not be used


in synthesizable code. They are
intended for use in simulation
testbenches only.
For
Loop:
For loops can be used in both synthesizable and non-synthesizable code.
For loops in synthesizable code are used to expand replicated logic. They are simply a way
of shrinking the amount of code that is written by the hardware designer.
Uploading program on
FPGA

1) Make sure you have compiled and simulated your program and checked its netlist and
simulation on Modelsim.
2)On your Menu Bar open Assignments-> Device.

3) After this on your menu bar open


Assignments-> Pin Planner
Uploading program on
FPGA

4) Compile the project again and then go to Tools->Programmer


•Tasks

• Write a Verilog program for binary to gray code converter


along with Testbench using System Functions
• Write a Verilog Program for ALU using case statement along
with Testbench using System Functions

module lab3tb;
reg a,b;
wire y;
LAB3 l1(a,b,y);
initial
$monitor("monitor at time %t -> a=%b, b=%b, y=%b", $time,a,b,y);
Initial begin
$display("display at time %t -> a=%b, b=%b, y=%b",$time,a,b,y);
#10;a=1'b0;b=1'b0;
$display("display at time %t -> a=%b, b=%b, y=%b",$time,a,b,y);
#10;a=1'b0;b=1'b0;
end
endmodule

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