Chapter Two
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Lesson-2 Outline
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• Atmel AVR
• Microchip’s PIC
• Freescale Semiconductor’s HCS08
• Intel’s 8051
• Zilog’s Z8
32-bit microcontrollers
• AVR32
• ARM
• PIC32
40 PIN DIP
(XCK/T0) PB0 1 40 PA0 (ADC0)
(T1) PB1 2 39 PA1 (ADC1)
(INT2/AIN0) PB2 3 38 PA2 (ADC2)
RAM EEPROM Timers
(OC0/AIN1) PB3 4 MEGA32 37 PA3 (ADC3)
PROGRAM (SS) PB4 5 36 PA4 (ADC4)
ROM (MOSI) PB5 6 35 PA5 (ADC5)
(MISO) PB6 7 34 PA6 (ADC6)
Program (SCK) PB7 8 33 PA7 (ADC7)
Bus Bus RESET 9 32 AREF
CPU
VCC 10 31 AGND
GND 11 30 AVCC
XTAL2 12 29 PC7 (TOSC2)
XTAL1 13 28 PC6 (TOSC1)
(RXD) PD0 14 27 PC5 (TDI)
Interrupt Other (TXD) PD1 15 26 PC4 (TDO)
OSC Ports
Unit Peripherals (INT0) PD2 16 25 PC3 (TMS)
(INT1) PD3 17 24 PC2 (TCK)
(OC1B) PD4 18 23 PC1 (SDA)
I/O (OC1A) PD5 19 22 PC0 (SCL)
PINS
(ICP) PD6 20 21 PD7 (OC2)
• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287
1. Vital Pins:
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1. Power
• VCC
• Ground
2. Crystal
• XTAL1
• XTAL2
3. Reset
2. I/O pins
• PORTA, PORTB,
PORTC, and PORTD
3. Internal ADC pins
• AREF, AGND, AVCC
• AVR’s CPU
– ALU
– 32 General Purpose
registers (R0 to R31)
– PC register
– Instruction decoder
– SREG
as input pins.
• All bits in these registers can be read as well as written to.
• The initial value of these bits is zero.
PORTx: Data Registers
• These are 8-bit registers.
• These are used to put the pins of the ports in
a logic HIGH or logic LOW state.
• Writing a one to the bits in this register
puts a HIGH logic (5V) on those pins.
• Whereas writing a zero to the bits in this
register puts a LOW logic (0V) on those pins.
• All bits in these registers can be read as
well as written to.
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• The initial value of these bits is zero.
Assembly and C System By Mikru L. JiT-JU Upper Saddle River, NJ 07458. • All Rights
GPIO
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• external crystal,
• external RESET button,
• additional components for AD converter
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Driving Loads – source or sink configurations
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Communication:
Parallel, USB/Serial, USART, SPI,
TWI, Ethernet, Wireless
B.Sc(SE), 2023
By Mikru L.
AVR Microcontroller and Embedded System Using © 2011 Pearson Higher Education,
Assembly and C Upper Saddle River, NJ 07458. • All Rights
Parallel vs. Serial
• Parallel
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• Synchronous
– Clock pulse should be transmitted during
data transmission.
– Only one side generates clock at the same
time.
• Asynchronous
– Clock pulse is not transmitted.
– The two sides should generate clock pulse.
– There should be a way to synchronize the
two sides.
drives, floppy
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anddrives,
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SPI (Serial
( Peripheral Interface )
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TWI-Connection
Ethernet Block
Diagram
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By Mikru L
AVR Microcontroller and Embedded System Using © 2011 Pearson Higher Education,
Assembly and C Upper Saddle River, NJ 07458. • All Rights
Interrupt
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AVR.
Pins PD2 (PORTD.2),
PD3 (PORTD.3),
PB2 (PORTB.2)
These are for the external hardware interrupts INT0, INT1,
and INT2, respectively
PROGRAMMING EXTERNAL HARDWARE
INTERRUPTS
The number of external hardware interrupt interrupts
varies in different AVRs.
There are three external hardware interrupts in the
ATmega32: INTO,SEng4033:
INT1, and INT2.
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External Interrupts
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effect.
These interrupts are controlled by the following registers.
GICR
GIFR
MCUCR
MCUCSR
GICR:
INT0:
When this bit is ‘1’ and global interrupt bit in SREG is
‘1’(i.e. I bit) the External Interrupt 0 is enabled.
The ISC01 and ISC00 of MUCR register control the
interrupt when to be
Systemactivated
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GICR:
The INTO is a low-level-triggered interrupt by default,
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which means,
when a low signal is applied to pin PD2 (PORTD.2), the
controller will be interrupted and jump to location
$0002 in the vector table to service the TSR.
INT1: When this bit is ‘1’ and global interrupt bit in
SREG is ‘1’ (i.e. I bit) the External Interrupt 1 is control
the interrupt when level sensed) enabled.
The ISC11 and ISC10 of MCUCR register to be activated
(i.e. on rising edge or falling edge or
INT2: When this bit is ‘1’ and global interrupt bit in
SREG is ‘1’ (i.e. I bit) the External Interrupt 2 is
enabled.
ISC2 bit of MCUCSR register control the interrupt when
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be andactivated (i.e. on Systemrising
By Mikru L.edge or falling
Saddle River, edge).
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MCUCR:
There are 2 types of activation for the external hardware
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interrupts.
Level triggered
Edge triggered
INT0 & INT1 can be edge or level triggered, but INT2
can be edge triggered only.
The MCUCR & MCUCSR registers decides the triggering
options of the external hardware interrupts INT0, INT1, and
INT2.
MCUCR:
This register decides the triggering options of the external
hardware interrupts INT0 and INT1.
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MCUCR:
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ISC11 &ISC10:
• These bits define the level or edge on the external INT1 pin
that activate the interrupt as shown in table below.
If the interrupt is active (the INTx bit is set and the I-bit in SREG
is one), the AVR will jump to the corresponding interrupt vector
location and the TFINx flag will be cleared automatically,
otherwise, the flag remains set. The flag can be cleared by
writing a one to it.
• In other words
• INTF1: When ‘1’ on this bit trigger INT1 Interrupt when INT1 bit
of GICR and I bit of SREG is one.
• INTF0: When ‘1’ on this bit trigger INT0 Interrupt when INT0 bit
of GICR and I bit of SREG is one.
• INTF2: When ‘1’ on this bitReal
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trigger INT2 Interrupt
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when INT265bit
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of GICR and I bit of SREG
Assembly and C
is one.
INTERRUPT PROGRAMMING IN C:
In C language there is no instruction to manage the
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interrupts.
So, in WinAVR the following have been added to manage
the interrupts:
Interrupt include file: We should include the interrupt
header file if we want to use interrupts in our program.
Use the following instruction:
#include <avr\ interrupt .h>
cli ( ) and sei ( ):
In Assembly, the CLI and SEI Instructions clear and
set the I-bit of the SREG register, respectively.
In WinAVR, the cli () and sei () macros do the same
tasks.
hardware.
Timer is used to generate delay and counter is
for counting external events.
There is small line between timer and counter which
differentiate them.
Timer/Counter module has internal counter
register, which plays an important role.
When we want to count events, we connect external
event (e.g. event : rising edge or falling edge) source
to input pin of timer/counter module.
When external event occurs the value of counter
increments.
Value of counter represents no. of external
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Timers in AVR
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• 1 to 6 timers
– 3 timers in ATmega32
• 8-bit and 16-bit timers
– two 8-bit timers and one 16-bit timer in
• So ATmega32
basically, a timer is a register! But not a normal
one.
• The value of this register increases/decreases
automatically.
• In an 8-bit timer, the register used is 8-bit wide
whereas in 16-bit timer, the register width is of 16
bits.
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Timers in AVR
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PSR10
Clear
clkIO 10-bit T/C Prescaler
clk/8
clk/64
clk/256
clk/1024
T0
0
CS00 0 1 2 3 4 5 6 7
CS01
CS02
Timer/Counter0 clock
source
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The Prescaler
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