Computer

Architecture
S O U RC E : C O M P U T E R O R G A N I Z AT I O N A N D A RC H I T E C T U R E 1 0 T H W I L L I A M S TA L L I N G
BY H O O R U L A I N
LECTURE # 2
Parts of Computer architecture
Structure: The way in which the components are interrelated.
 Physical components: Memory, CPU, Control unit, ALU, registers, buses
Functions: The operation of each individual component as part of the structure.
Data processing :Data may take a wide variety of forms, and the range of processing
requirements is broad.
 Data storage: Even if the computer is processing data on the fly must temporarily store at least
those pieces of data that are being worked on at any given moment.
 Data Movement: OS consists of devices that serve as either sources or destinations of data.
<1> data from or delivered to a device that is directly connected to the computer, the process is
known as input–output(I/O), and device =>peripheral.
 Control: Within the computer, a control unit manages the computer’s resources and
orchestrates the performance of its functional parts in response to instructions.
Simple Single processor
computer (Structure)
Cont..
Part 1:
I/O: Moves data between the computer and its external environment.
System interconnection: Some mechanism that provides for communication among CPU,
main memory, and I/O.
System bus: A common example of system interconnection is by means of a consisting of a
number of conducting wires to which all the other components attach.
Part 2: Its major structural components are as follows:

Control unit: Controls the operation of the CPU and hence the computer.
Arithmetic and logic unit (ALU): Performs the computer’s data processing
functions.
Registers: Provides storage internal to the CPU.
CPU interconnection: Some mechanism that provides for communication
among the control unit, ALU, and registers.

Part 3: It covers these components, where we will see that complexity is added by the use of parallel and pipelined
organizational techniques. Finally, there are several approaches to the implementation of the control unit; one
common approach is a microprogrammed implementation.
Types of Architectures
The different architectural categories found in our computer systems are as follows:
Von-Neumann Architecture
Harvard Architecture
Instruction Set Architecture
Micro-architecture
Von Neuman Architecture
Von-Neumann computer architecture design was proposed in 1945.It was later known as Von-
Neumann architecture.
Basic structure is shown in following figure:
It is also known as ISA (Instruction set architecture) computer and is having three basic units:
 The Central Processing Unit (CPU)
 The Main Memory Unit
 The Input/Output Device.
 Cont…
1. Central Processing Unit: The central processing unit is defined as the it is an electric circuit used for the executing the
instruction of computer program.
It has following major components:
1.1 Control Unit(CU): A control unit (CU) handles all processor control signals. It directs all input and output flow, fetches code
for instructions, and controls how data moves around the system.
1.2 Arithmetic and Logic Unit(ALU): The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU
may need, e.g. Addition, Subtraction, Comparisons. It performs Logical Operations, Bit Shifting Operations, and Arithmetic
operations.
1.3. Variety of Registers :
1.4 Buses: Buses – Data is transmitted from one part of a computer to another, connecting all major internal components to the
CPU and memory, by the means of Buses. Types:
◦ Data Bus: It carries data among the memory unit, the I/O devices, and the processor.
◦ Address Bus: It carries the address of data (not the actual data) between memory and processor.
◦ Control Bus: It carries control commands from the CPU (and status signals from other devices) in order to control and coordinate all the
activities within the computer.
Harvard Architcture
The Harvard architecture refers to a computer architecture with distinct data and instruction
storage and signal pathways. In contrast to the von Neumann architecture, in which program
instructions and data use the very same memory and pathways, this design separates the two.
In practice, a customized Harvard architecture with two distinct caches is employed (for data
and instruction); X86 and Advanced RISC Machine (ARM) systems frequently employ this
instruction.
ISA(instruction set architecture)
The ISA defines the types of instructions to be supported by the processor.
Based on the type of operations they perform MIPS Instructions are classified into 3 types:
◦ Arithmetic/Logic Instructions:
These Instructions perform various Arithmetic & Logical operations on one or more operands.
◦ Data Transfer Instructions:
These instructions are responsible for the transfer of instructions from memory to the processor registers and vice versa.
◦ Branch and Jump Instructions:
These instructions are responsible for breaking the sequential flow of instructions and jumping to instructions at various
other locations, this is necessary for the implementation of functions and conditional statements.
The ISA defines the maximum length of each type of instruction. Since the MIPS is a 32 bit ISA, each instruction must be
accommodated within 32 bits.
The ISA defines the Instruction Format of each type of instruction.
The Instruction Format determines how the entire instruction is encoded within 32 bits
There are 3 types of Instruction Formats in the MIPS ISA:
◦ R-Instruction Format
◦ I-Instruction Format
◦ J-Instruction Format
Comparison of ISA and
Microarchitecture
Instruction Set Architecture Microarchitecture

The ISA is responsible for defining the set of instructions to be The Microarchitecture is more concerned with the lower level
supported by the processor. For example, some of the instructions implementation of how the instructions are going to be executed
defined by the ARMv7 ISA are given below. and deals with concepts like Instruction Pipelining, Branch
Prediction, Out of Order Execution.

On the other hand, the Branch of Computer Organization is

concerned with the implementation of a particular ISA deals with
The Branch of Computer Architecture is more inclined towards various hardware implementation techniques, i.e. is the
the Analysis and Design of Instruction Set Architecture. For Microarchitecture level. For Example, ARM licenses other
Example, Intel developed the x86 architecture, ARM developed companies like Qualcomm, Apple for using ARM ISA, but each of
the ARM architecture, & AMD developed the amd64 architecture. these companies have their own implementations of this ISA
The RISC-V ISA developed by UC Berkeley is an example of an thereby making them different in performance and power
Open Source ISA. efficiency. The Krait cores developed by Qualcomm have a
different microarchitecture and the Apple A-series processors
have a different microarchitecture.
Other categories of Architecture
1. CISC: The current x86 offerings represent the results of decades of design effort on complex
instruction set computers (CISCs).The x86 incorporates the sophisticated design principles
once found only on mainframes and supercomputers and serves as an excellent example of
CISC design.

2. RISC: An alternative approach to processor design is the reduced instruction set computer
(RISC). The ARM architecture is used in a wide variety of embedded systems and is one of
the most powerful and best-designed RISC-based systems on the market.
Evolution of Different
architectures
■ 8080: The world’s first general- Purpose microprocessor. This was an 8-bit machine, with an
8-bit data path to memory. The 8080 was used in the first personal computer, the Altair.
■ 8086: A far more powerful, 16-bit machine. In addition to a wider data path and larger
registers, the 8086 sported an instruction cache, or queue, that prefetches a few instructions
before they are executed. A variant of this processor, the 8088, was used in IBM’s first personal
computer, securing the success of Intel. The 8086 is the first appearance of the x86 architecture.
■ 80286: This extension of the 8086 enabled addressing a 16-MB memory instead of just 1 MB.
■ 80386: Intel’s first 32-bit machine, and a major overhaul of the product. With a 32-bit
architecture, the 80386 rivaled the complexity and power of minicomputers and mainframes
introduced just a few years earlier. This was the first Intel processor to support multitasking,
meaning it could run multiple programs at the same time.
 Cont..
■ 80486: The 80486 introduced the use of much more sophisticated and powerful cache technology and sophisticated instruction
pipelining. The 80486 also offered a built- n math coprocessor, offloading complex math operations from the main CPU.
■ Pentium: With the Pentium, Intel introduced the use of superscalar techniques, which allow multiple instructions to execute in
parallel.
■ Pentium Pro: The Pentium Pro continued the move into superscalar organization begun with the Pentium, with aggressive use of
register renaming, branch prediction, data flow analysis, and speculative execution.
■ Pentium II: The Pentium II incorporated Intel MMX technology, which is designed specifically to process video, audio, and graphics
data efficiently.
■ Pentium III: The Pentium III incorporates additional floating- point instructions: The Streaming SIMD Extensions (SSE) instruction set
extension added 70 new instructions designed to increase performance when exactly the same operations are to be performed on
multiple data objects. Typical applications are digital signal processing and graphics processing.
■ Pentium 4: The Pentium 4 includes additional floating- point and other enhancements for multimedia.11
■ Core: This is the first Intel x86 microprocessor with a dual core, referring to the implementation of two cores on a single chip.
■ Core 2: The Core 2 extends the Core architecture to 64 bits. The Core 2 Quad provides four cores on a single chip. More recent Core
offerings have up to 10 cores per chip. An important addition to the architecture was the AdvancedVector Extensions instruction set
that provided a set of 256-bit, and then 512-bit, instructions for efficient processing of vector data.