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Layout

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14 views12 pages

Layout

Uploaded by

Gourika Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Layout Design rules

Layout design rules


• The rules are defined in terms of feature sizes (widths), separations,
and overlaps.
• The main objective of the layout rules is to build reliably functional
circuits in as small an area as possible. Design rules specify to the
designer certain geometric constraints on the layout artwork so that
the patterns on the processed wafer will preserve the topology and
geometry of the designs.
• Design rules based on the MOSIS(Meatal Oxide Semiconductor
Implementation System) CMOS scalable rules. The MOSIS rules are
expressed in terms of lamda.
Well rules

• The n-well is usually a deeper implant (especially a deep n-well) than the transistor source/drain
implants, and therefore, it is necessary to provide sufficient clearance between the n-well edges
and the adjacent n+ diffusions.
• The clearance between the well edge and an enclosed diffusion is determined by the transition of
the field oxide across the well boundary.
• Mask Summary: The masks encountered for well specification may include n-well, p-well, and
deep n-well. These are used to specify where the various wells are to be placed. Often only one
well is specified in a twin-well process (i.e., n-well) and by default the p-well is in areas where the
n-well isn’t (i.e., p-well equals the logical NOT of the n-well)
Transistor Rules
• CMOS transistors are generally defined by at least four physical masks. These are active (also
called diffusion, diff, thinox, OD, or RX), n-select (also called n-implant, nimp, or nplus), p-select
(also called p-implant, pimp, or pplus) and polysilicon (also called poly, polyg, PO, or PC).
• It is essential for the poly to cross active completely; otherwise the transistor that has been
created will be shorted by a diffusion path between source and drain. Hence, poly is required to
extend beyond the edges of the active area. This is often termed the gate extension. Active must
extend beyond the poly gate so that diffused source and drain regions exist to carry charge into
and out of the channel. Poly and active regions that should not form a transistor must be kept
separated; this results in a spacing rule from active to polysilicon.
• Mask Summary: The basic masks (in addition to well masks) used to define transistors, diffusion
interconnect (possibly resistors), and gate interconnect are active, n-select, p-select, and
polysilicon. These may be called different names in some processes. Sometimes n-diffusion
(ndiff ) and p-diffusion (pdiff ) masks are used in place of active to alleviate designer confusion.
Contact rules:
Contact rules Substrate contact
There are several generally available contacts:
• Metal to p-active (p-diffusion)
• Metal to n-active (n-diffusion)
• Metal to polysilicon
• Metal to well or substrate

• Depending on the process, other contacts such as buried polysilicon-active contacts may be allowed
for local interconnect.
• Because the substrate is divided into well regions, each isolated well must be tied to the appropriate
supply voltage; i.e., the n-well must be tied to VDD and the substrate or p-well must be tied to GND
with well or substrate contacts.
• Whenever possible, use more than one contact at each connection. This significantly improves yield
in many processes because the connection is still made even if one of the contacts is malformed.
• Mask Summary: The only mask involved with contacts to active or poly is the contact mask,
commonly called CONT or CA. Contacts are normally of uniform size to allow for consistent etching
of very small features
Metal Rules:
• Metal spacing may vary with the width of the metal line (so called fat-
metal rules).
• Metal rules may be complicated by varying spacing dependent on
width: As the width increases, the spacing increases. Metal overlap
over contact might be zero or nonzero.
Via Rules:
• Processes may vary in whether they allow stacked vias to be placed
over polysilicon and diffusion regions.
• Some processes allow vias to be placed within these areas, but do not
allow the vias to straddle the boundary of polysilicon or diffusion. This
results from the sudden vertical topology variations that occur at
sublayer boundaries.
• Modern planarized processes permit stacked vias, which reduces the
area required to pass from a lower-level metal to a high-level metal.
• Mask Summary: Vias are normally of uniform size within a layer. They
may increase in size toward the top of a metal stack. For instance,
large vias required on power busses are constructed from an array of
uniformly sized vias
Other rules:
• The passivation or overglass layer is a protective layer of SiO2 (glass)
that covers the final chip. Appropriately sized openings are required at
pads and any internal test points.
Some additional rules that might be present in some processes are as
follows:
• Extension of polysilicon or metal beyond a contact or via
• Differing gate poly extensions depending on the device length
• Maximum width of a feature
• Minimum area of a feature (small pieces of photoresist can peel off and
float away)
• Minimum notch sizes (small notches are rarely beneficial and can
interfere with resolution enhancement techniques)
Contact rules:
Micron design rules for 65 nm
process:

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