ENSC-252

Fundamentals of Digital Logic & Design

Fall 2024

November 16, 2024 1

Synchronous Sequential Circuits: Lecture outline
o Design techniques for circuits that use flip-flops

o The concept of states and their implementation with flip-flops

o Synchronous control by using a clock signal

o Sequential behavior of digital circuits

o A complete procedure for designing synchronous sequential circuits

o VHDL specification of sequential circuits

o The concept of finite-state machines

Fundamentals of Digital Logic with VHDL Design 4th edition, Stephen Brown | Zvonko Vranesic, McGraw-Hill
Digital Design, by M. Morris Mano | Michael D. Ciletti

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Synchronous Sequential Circuits
Inputs
Sequential logic circuits Combinational Outputs
circuit Memory
 Synchronous elements
 Asynchronous

The current state of the system is feedbacked as inputs to the system.

Determining next Determining next
state S(t+1) Present state S(t) state S(t+1) Present state S(t)

Inputs Outputs Inputs Outputs

Combinational Combinational Combinational Combinational
circuit
Flip-Flops circuit circuit
Flip-Flops circuit

CLK CLK
Qs Qs

Moore type synchronous sequential circuits Mealy type synchronous sequential circuits
Invented by Edward F. Moore Invented by George H. Mealy
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Synchronous Sequential Circuits
• Synchronization is provided by using a timing signal called clock
• Clock signal is distributed throughout the whole design
• Each component is synchronized with the clock
Synchronous sequential circuit
Rising edge of clock Falling edge of clock
Inputs Outputs
Combinational
circuit State
𝑇 𝑐𝑙𝑘 Defining flip-flops
Clk next state Clk
clk
𝑇 𝑐𝑙𝑘 ≥ 𝑡 𝑐𝑄 , 𝐹𝐹 +𝑡 𝑝𝑑, 𝑐𝑜𝑚𝑏 +𝑡 𝑠𝑢
Present state

• During each clock period, the storage elements (FFs) hold (keep) the present state of the sequential circuit to be
used for determining (calculating) the next state and the current output of the system.
• The input of the storage elements define the state of the system at the next clock period (next state).

In general, any sequential circuit with 2n-1 < k <2n states requires n bit storage elements with feedback lines.

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Synchronous Sequential Circuits
o State Equations: A state equation (also called a transition equation) specifies the next state as a function of the present
state and inputs. Combinational logic circuit Storage elements
Example:
• Inputs: x(t) or x
𝐷𝐴
• Present state variables (FFs outputs):
A(t) or A, B(t) or B

• Next state variables (FFs outputs):

A(t+1) or A*, B(t+1) or B*
The next states values are determined based on the FFs inputs
A(t + 1) = DA and B(t + 1) = DB 𝐷𝐵

• Outputs: y(t) or y

DA = A(t).x(t) + B(t).x(t)
DB = A’(t).x(t)

A(t + 1) = A(t).x(t) + B(t).x(t)

B(t + 1) = A’(t).x(t) y(t) = [A(t) + B(t)]x’(t)
Mealy or Moore?
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Synchronous Sequential Circuits
State table: contain the following four sections
• Present state: the values of the state variables used by the combinational circuit at the preset clock period
• Inputs: the input combinations come from outside
• Next state: the values of the state variables at the next clock period (t+1). Determined based on the FF inputs
at the present time.
• Outputs: the outputs of the circuit go to outside

Example:
A(t + 1) = A.x + B.x y = (A + B)x’
B(t + 1) = A’ x

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Synchronous Sequential Circuits
State diagram: The function of a sequential circuit (state machine) can be represented in a graphical form called state
diagram with the following components:

• A circle for each state with the state code or name in it

• A directed arc from the Present State to the Next State for each state transition at the active edge of CLK
• A label on each directed arc with the Input values, which leads to that state transition at CLK active edge
• A label with the produced output value I/O
 On each Directed arc (Mealy state machine)
S1 S2
or
 In each circle (Moore state machine) I

S1/O1
S2/O1

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Synchronous Sequential Circuits
Mealy State Machine:
Output = f ( state, inputs )
Read as: When we are at the state S1 and the input I is applied we get the output
I/O
O and after the upcoming active clock edge, we will proceed to the state S2.
S1 S2
State table
Example: create a state diagram for the following state table. Present state Input Next state Output
A(t) B(t) X(t) A(t+1) B(t+1) y(t)
0/0 1/0 0 0 0 0 0 0
0 0 1 0 1 0
00 01
0/1 A(t + 1) = A.x + B.x 0 1 0 0 0 1
B(t + 1) = A’ x
0/1 1/0 y = (A + B)x’ 0 1 1 1 1 0
0/1 1 0 0 0 0 1
10 11 1 0 1 1 0 0

1/0 4 possible states: {00, 01, 10, 11} 1 1 0 0 0 1

1/0
Two FFs are needed to implement this SD. 1 1 1 1 0 0

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Synchronous Sequential Circuits
Moore State Machine:
Output = f ( state)
Read as: When we are at the state S1 with the output O1 and the
I input I is applied, after the upcoming active edge of clock we will
proceed to the state S2 with output O2.
S1/O1
S2/O1
State table
Present state Input Next state Output
Example: create a state diagram for the following state table. A(t) x(t) y(t) A(t+1) z(t)
0 0 0 0 0
00,11 0 0 1 1 0
00,11
01,10 A(t + 1) = A  x  y
0 1 0 1 0
0/0 1/1 z = A(t)
0 1 1 0 0
1 0 0 1 1
01,10
1 0 1 0 1
2 possible states: { 0, 1 } 1 1 0 0 1
One FF is needed to implement this SD. 1 1 1 1 1

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Synchronous Sequential Circuits: Analyzing procedure
To analyze a sequential circuit
1) Obtain the input equations for each FFs (for determining the next state) using the present state and input variables.
2) Then, use the corresponding flip-flops characteristic tables to determine the next state, and then, fill the state table
3) Obtain the output equations based on the present state and/or inputs and fill the state table.
4) Draw the state diagram based on the state table.
Present state (A(t))
Example: Analyze the following DFF-based sequential circuit.

x
Inputs
y 𝐷𝑄 z
Output
Clk
CLK z = A(t)
𝑄
It determines the Next State (A(t+1) or A*) that will be our Q(t+1)=D
present state after the upcoming active CLK edge.
Logic diagram
A(t + 1) = A  x  y

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Synchronous Sequential Circuits: Analyzing procedure
Example: Analyze the following DFF-based sequential circuit and draw a state diagram for the circuit.
𝐷𝐴
Variables: Flip-flops input equations 𝐷 𝑄𝐴 𝑍
• Inputs: None Clk
• State variables: A, B, C
• Outputs: Z = A
𝐷𝐵
Initialization 𝐷 𝑄𝐵
• Reset to (0, 0, 0) by clear Clk
State table
Present state Next state Output
𝐷𝐶
A(t) B(t) C(t) A(t+1) B(t+1) C(t+1) z(t) 𝐷 𝑄𝐶
0 0 0 0 0 1 0
Clk
0 0 1 0 1 0 0
0 1 0 0 1 1 0
𝑐𝑙𝑘
0 1 1 1 0 0 0
1 0 0 0 0 0 1 𝑐𝑙𝑟
1 0 1 0 1 0 1
1 1 0 0 1 0 1
1 1 1 1 0 0 1 3 FFs, 8 possible states
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Synchronous Sequential Circuits: Analyzing procedure
Example: Continued.
State diagram
State table
Present state Next state Output ABC/Z
A(t) B(t) C(t) A(t+1) B(t+1) C(t+1) z(t) Clear 000/0
001/0
0 0 0 0 0 1 0
0 0 1 0 1 0 0
0 1 0 0 1 1 0
0 1 1 1 0 0 0
111/1 100/1 010/0 101/1
1 0 0 0 0 0 1
1 0 1 0 1 0 1
1 1 0 0 1 0 1
1 1 1 1 0 0 1 011/0
110/1

What is the function of this circuit?

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Synchronous Sequential Circuits: Analyzing procedure
Example: Analyze the following JKFF-based sequential circuit and draw a state diagram for the circuit.
Variables:
𝑄 𝐴
𝐽𝐴
Flip-flops input equations 𝐽
• Inputs: x 𝑥
• State variables: A, B
𝐾𝐴
𝐾
• Outputs: Z = B
Initialization 2 FFs, 4 possible states 𝐽𝐵
• Reset to (0, 0) by clear
𝐽 𝑄𝐵 𝑧
State table
𝐾𝐵
𝐾
Present state Input FFs inputs Next state Output
A(t) B(t) x(t) A(t+1) B(t+1) z(t)
0 0 0 0 0 1 0 0 1 0 𝑐𝑙𝑘
Mealy or Moore?
0 0 1 0 0 0 1 0 0 0 𝑐𝑙𝑟
0 1 0 1 1 1 0 1 1 0
0 1 1 1 0 0 1 1 0 0
1 0 0 0 0 1 1 1 1 1 0 0 Q(t) No change (Hold)
1 0 1 0 0 0 0 1 0 1 0 1 0 Reset
1 1 0 1 1 1 1 0 0 1 1 0 1 Set
1 1 1 1 0 0 0 1 1 1 1 1 Q’(t) Complement
The inputs of the FFs determine the next state. JK-FF characteristic table
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Synchronous Sequential Circuits: Analyzing procedure
Example: Continued
State table State diagram
Present state Input FFs inputs Next state Output
1 0
A(t) B(t) x(t) A(t+1) B(t+1) z(t)
0 0 0 1 0 0 1
0 0 0 Clear 00/0 01/1
1 0 0 0 1 0 0
0 1 1 1 0 1 1
0 1 0
1 1 0 0 1 1 0 0 1
0 0 0 1 1 1 1 0
1 0 1
1 0 0 0 0 1 0
11/1 10/1
0 1 1 1 1 0 0
1 1 1
1 1 0 0 0 1 1 0 1
1

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Synchronous Sequential Circuits: Analyzing procedure
Example: Analyze the following JKFF-based sequential circuit and draw a state diagram for the circuit.
Variables:
• Inputs: x Mealy or Moore?
• State variables: A, B ′ ′
𝑧=𝐵 𝑥 + 𝐴𝑥+ 𝐴 𝐵𝑥′
• Outputs: Z =
Initialization 𝐽𝐴
𝐽 𝑄𝐴
• Reset to (0, 0) by clear
𝐾𝐴
𝐾 𝑄′ 𝑧
Flip-flops input equations
𝑥
𝐽𝐵
𝐽 𝑄𝐵

𝐾𝐵
𝐾 𝑄′
2 FFs, 4 possible states

𝑐𝑙𝑘
𝑐𝑙𝑟

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Synchronous Sequential Circuits: Analyzing procedure
Example: Continued.
• Outputs: Z = 0 0 Q(t) No change (Hold)
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement

JK-FF characteristic table

0/0
State diagram
State table
Present state Input FFs inputs Next state Output
z(t) 0/0
1/1 𝑆2
A(t) B(t) x(t) A(t+1) B(t+1) 1/1
0 0 0 0 0 0 0 0
0 0
1 0 1 1 0 0 1 1 Clear 𝑆0 𝑆1
0 0 0 0 0 0 1 1 0/1
0 1
1 1 1 1 0 1 1 0
0 0 0 0 0 1 0 0 1/0
1 0 1/1
1
0
0 1 1 1
0 0 0 0
0
1
1
1
1
0
𝑆3
1 1
1 1 1 1 1 0 0 1
0/0
The inputs of the FFs determine the next state.
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 Questions?

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