Scribd
Upload
9 views

Lab1-Introduction Verilog

Uploaded by

Ayan Shaikh
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
9 views

Lab1-Introduction Verilog

Uploaded by

Ayan Shaikh
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 7

CLPD Lab

LAB 1. Introduction to Verilog HDL


Verilog Code
Structure:

• Data Flow Modeling Style:


Task
1:
Write a Verilog code of Half Adder using Dataflow Modelling

module half_adder ( a, b, sum, carry ) ;

input a, b ;
output sum, carry ;

assign sum = a ^ b ;
assign carry = a & b ;

endmodule
Write a Verilog code of Half Adder using structural Modelling

module HalfAdder(a,b,sum,carry);

input a,b;
output sum,carry;

xor x1(sum,a,b);
and a1(carry,a,b);

endmodule
• Simple Testbench:  Testbench is written to check the functionality
of the design module.

 From the testbench we drive the input


stimulus to our design and check the
output response to the given input.

 So, for the testbench


 Input : Will be the output of design
module( also known as Design Under
Test- DUT)

 Output: will be the input to design


module (DUT)

 Point to NOTE:
 DUT input list will be define as “reg”
type inside the testbench.

 DUT output list will be define as “wire”


type inside the testbench.
Verilog
:

 “#” used to specify the delay in the simulation

 NOTE: synthesis tool will ignore any kind of “#” specified delays
Task 2
:

1. Draw TT and simplify using k-maps if a 3 input function has conditions that
output is high if inputs has exactly 2 zeros or exactly 2 ones

2. In a factory, if relay A is ON then indicator glows except condition that if both B


and C are ON, and if A is OFF then indicator glows only when relay D is ON. Find
the TT and simplify using k-map.

(20mins)

You might also like