8085 MEMORY

MEMORY SYSTEM of 8085

• Memory is an essential component of a microcomputer
system. The memory could be R/W memory and Read
Only memory (ROM).
• The R/W memory is made up of registers and each
register has a group of flip-flops or field-effect transistors
that stores bits of information, these flip-flops are called
memory cells.
• The number of bits stored in a register is called a
“memory word”.
• The users can use these memories to hold programs and
hold data.
• On the other hand, ROM stores information permanently
in the form of diodes; the group of diodes can be viewed
as a register.
• In a memory chip, all registers are arranged in a sequence
and identified by binary numbers called memory
addresses.
 Flip-Flop or Latch as a Storage
Element
• What is memory? It is a circuit that can store bits – high or
low, generally voltage levels or capacitive charges
representing 1 or 0.
• A flip-flop or latch is basic element of memory.

• To write or store a bit in the latch, we need an input data

bit (DIN) and an enable signal (EN); Fig (a). Here store bit is
always available on the output line DOUT.
• To avoid unintentional change in the input and control the
availability of the output, we can use two tristate buffer on
the latch; fig (b).
 Flip-Flop or Latch as a Storage
Element
• In the latch with tristate buffer, we can write into
the latch by enabling input buffer and read from it
enabling output buffer.
• The Write signal ( and read ( signals are active low
signals indicated by the bar.
• This latch which can store one binary bit is called a
memory cell.
Flip-Flop or Latch as a Storage
Element

• Four latches grouped

together to form a
register that can
store 4 bits.
• Size of register is
specified as 4-bit or
1x4 bit; one register
with 4 cells or four
I/O lines.
Flip-Flop or Latch as a Storage
Element
Flip-Flop or Latch as a Storage
Element
Two Memory Chips with Four Register Each &
Chip Select
8085 MEMORY
8085 MEMORY
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
 MEMORY MAP & ADDRESSES
• The memory chip has 256 registers
and 8 I/O lines, so the size of memory
chip is 256x8.
• It has eight address lines (A0-A7), one
Chip Select (CS) signal, and two
control signals, Read and Write (both
active low).
• The A0-A7 address line will identify
256 memory registers
• Remaining A8-A15 lines are connected
to CS through inverters and NAND
gate. when CS goes low; therefore, all
• Memory chip gets enabled
the lines (A8-A15) should be at logic zero to select the chip.
No other logic combination will enable the chip.
• Once the chip is selected, the remaining lines (A0-A7) can
assume any combination from 0000H to 00FFH to identify
any of the 256 memory registers through the decoder.
 MEMORY MAP & ADDRESSES
• Therefore, the memory address for the chip in Fig (a) will
range from 0000H to 00FFH as below:

A7 A6 A5 A4 A3 A2 A1 A0 Memory Location
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 2
0 0 0 0 1 0 0 0 8
1 1 1 1 1 1 1 0 254 (00FEH)
1 1 1 1 1 1 1 1 255 (00FFH)

• The A8-A15 will be always fixed to zero logic for chip

MEMORY MAP & ADDRESSES
 MEMORY MAP & ADDRESSES
• The chip select addresses are determined by the hardware (the
inverters and NAND gate); therefore the memory addresses of the
chip can be changed by modifying the hardware.
• For example, if the inverter in the line A15 is removed, as shown in
Fig (b), the address required on A15-A8 to enable the chip will be as
follows:

• Here, the memory address range will be

from 8000 H to 80FFH.
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
MEMORY MAP & ADDRESSES
Memory & Instruction Fetch
Memory & Instruction Fetch
Memory Classification
Memory Classification: RAM
Memory Classification: DRAM (Dynamic
RAM)
Memory Classification: SRAM (Static
RAM)
Memory Classification: ROM (Read Only
Memory)
Memory Classification: Masked ROM
PROM: Programmable ROM
EPROM: Erasable Programmable ROM
EEPROM: Electrically Erasable
Programmable ROM
Flash Memory
Secondary Memory
 Input and Output Devices
• Input/output devices are the means through which MPU
communicates with the “outside world”.

• The MPU accepts binary data as input from devices such as

keyboard and A/D converters and send data to output
devices such as LEDs or printers.

• There are two different mode by which I/O device can be

identified; one by use of 8-bit address and the other by
using 16-bit address.
 I/O with 8-bit Addressed (Peripheral-
mapped I/O)
• This is an 8-bit numbering system for I/Os in conjunction
with Input and Output instruction.

• This is also called I/O space, separate from memory space

which is 16 bit numbering system.

• The 8 address line can have 256 (2^8 combination) address;

thus MPU can identify 256 input devices and 256 output
devices with address ranging from 00H to FFH.

• The Input and Output devices are differentiated by control

signals.
• The MPU used I/O Read control signal for input devices and
I/O Write control signal for Output devices.

• The entire range of I/O address from 00 H to FF H is known

as I/O map, and individual address are referred to as I/O
device address or I/O port number.
 I/O with 8-bit Addressed (Peripheral-
mapped I/O)
• If we use LEDs as output or switches as input device, we
need to resolve two issues:
• How to assign address
• How to connect these I/O device to data bus

• In the bus architecture, these devices can not be connected

directly to the data bus or address bus.

• All connection must be made through tri-state interfacing

device so they will be enabled and connected to the buses
when the MPU chooses to communicate with them.
 I/O with 8-bit Addressed (Peripheral-
mapped I/O)
• The steps in communicating with an I/O device are similar
to those in communicating with memory and can be
summarized as below:
• The MPU places an 8-bit address on the address bus,
which is decoded by external decoder logic.
• The MPU sends a control signal (I/O read or I/O write)
and enables the I/O device.
• Data are transferred using data bus.
I/O with 16-bit Addressed (Memory-
mapped I/O)
Example of Microcomputer System
 Example of Buffer

• This is also known as line driver

or line receiver.
• This device is commonalty
used as driver for the address
bus in a bus-oriented system.
• This device has two group of
four buffers with noninverted
tri-state output.
• Two control signals (1G and
2G), both active low.
• Until these lines are enabled,
the output of the buffers
remains in high impedance
state.
The Octal Buffer 74LS244
 BIDIRECTIONAL BUFFER
• The data bus of MPU system is bidirectional; therefore it
requires a buffer that allows data to flow in both the
directions.
 BIDIRECTIONAL BUFFER
• The 74LS245 includes 16 bus driver, eight for each
direction, with tri-state output.
• The direction of data flow is controlled by DIR.
• When DIR is high, data flow from the A bus to B bus; when it
is low data flow from B to A bus.
• The schematic also includes an ENABLE signal (G bar) which
is active low.
• The Enable signal and the DIR signal are ANDed to activate
the bus lines.
DECODERS
ENCODER