Slides that I have added to this ppt are: 12, 13, 14, 20, 21, 22, 24, 25,

26, 31, 32,

40(diagram), 41(diagram), 69, 70, 71, 72, 76, 77, 78, 79, 82, 83, 84, 85.
MBIST

2
Agenda
• Embedded memories

• Memory testing methods

• MBIST Basic (Architecture , modes, algorithm and addressing)

• Memory fault modeling

• MBIST w.r.t. MentorGraphics

• MBIST controllers types
• MBIST architecture and operating protocol
• Types of comparators
• Diagnostic
• MBIST LV flow
• ETVerify

• Check List

• Questions
3
What is Embedded
• Memory is consideredmemory?
embedded if some or all of its
terminals are not directly connected to the pins of the
chip

4
Memory testing methods

5
Direct Access Method

6
Direct Access Method(Contd..)
Entails (require) routing all of the embedded memory’s
inputs and outputs directly to the host chip’s pins

Multiplexing logic is used to choose between this routing

during test mode and the functional paths

So amount of extra interconnect required for this routing

can become prohibitive

Interconnect typically must be routed over large portions

of the chip & also increase propagation delay

Number of memory inputs and outputs might be larger

than the number of chip-level signal pins
7
Scan chain / ATPG method

8
Scan chain / ATPG method (Contd...)
Entails placing a scan chain around the embedded
memory
required

Added scan chain provides the capability of

scanning in test patterns and scanning out test
responses

Test application time can grow , because the test

patterns and responses need to be scanned in and
out

Because the test patterns cannot be applied to the

embedded memory on a cycle-by-cycle basis, an at-
speed test of the memory cannot be performed

9
MBIST Method

10
MBIST Method (Contd …)
Here we generates & apply the different/necessary
patterns and analyze the result’s of the embedded
memories

MBIST (Memory built in self test) embeds much of the

tester functionality into the device itself and it reduces
the cost/time of testing

Local BIST controller is used to generate the test

patterns and observe the test responses(pass/fail w.r.t.
memory defective cells) from the memory

Multiplexing logic chooses between address and data

originating from the BIST controller or from the system
logic

MBIST increases area overhead

11
BIST

• Useful for field test and diagnosis

• Less expensive than ATE
• Lower system test effort
• Improved system maintenance and repair
• Better diagnosis at component level
Costs involved in BIST

• Chip area overhead for Test controller,

Hardware pattern generator and response
compacter
• Pin Overhead i.e., at least 1 pin needed to
activate BIST operation
• Performance Overhead i.e., extra path delays
due to BIST
• Yield loss due to increased chip area
BIST Architecture
MBIST basic

15
 • Goal of memory testing is to provide high quality manufacturing tests
Introduction
for the memory by applying different patterns to determine defective
cells
• There could be different types of memory/arrays (SRAM's, CAM's,
ROM's and register files) and MBIST targets all of these array’s
• MBIST (Memory built in self test) embeds much of the tester
functionality into the device itself and it reduces the cost/time of
testing
• MBIST is integrated and automated test solution which supports
testing of memory where there is no connection to the ATE (output
pin) or outside testers location
• By default after power-on MBIST will run all patterns and give
pass/fail
• Master-slave architecture with a common master MBIST controller
• MBIST-slave controllers can test multiple arrays
• Slave controller to array communication can either be a ring or a star
topology
• JTAG (TAP) can be used to program the configuration register of the
MBIST master controller
• Each macro /array/ memory required valid cluster_id (i.e. For
identification)
• Memory can be single read/write port or Multiple ports
• MBIST provides the control interface for running Manufacturing and 16
In-System BIST
MBIST Architecture

Memory 1

Memory 2
Slave / Interface
TAP MBIST Controller ckt
/ collared

Memory n
MBIST Architecture
Sharing a BIST Controller Among Several Embedded Memories

19
BIST- Ready Memory
 Optimization:
- testing time 
SoC BIST -
-
memory cost 
power consumption 
- hardware cost 
- test quality 

Embedded Tester
Core 1 Core 2

Test Test access

Controller BIST mechanism BIST

Tester
Memory
BIST BIST BIST

Core 3 Core 4 Core 5

System on Chip
Full Chip Memory BIST Architectures
SOC
TM S Block
BIST Block
TCK TAP Controller
TRST
Memory 1
rst_l

BIST
CLK Controller
BIST Block
test_done

fail_h Memory 2

test_h

MBIST Data
Register
TDO
TDI Boundary Scan Register
 Sharing a BIST Controller Among Several Embedded Memories
(Contd…)
• Parallel Testing

• Advantage of testing the memories in parallel is a

reduced test time

• Power consumption that results from testing several

memories together can be high

• Certain BIST controller resources must be duplicated

• Serial Testing

Requires only one data line to be routed to each

embedded memory, regardless of the memory’s data
width

 Data values for each test pattern are provided serially

to the memory
23
 LogicVision’s Patented Serial BIST Approach for
Embedded Memories

Uses the memory itself to shift the incoming data bits across the data
width of the memory.
Configurations Overview
Sequential Testing of multiple memories Multiple RAMs in a parallel configuration

A single RAM in a parallel configuration Chained memory configuration of 3 RAMs

Memory Cores row/column architecture

1Kx32 memory (blocks) with 4:1 column multiplexing

Number of words = 1024 , number of bits in word = 32.

number of rows = 256 , number of column = 128.
ncolmux = number of words per row = 4
• Normal MBIST : Execution upon reset and run predefined MBIST
algorithm, referred to as normal MBIST
• RAM Testing: Operatin
• Read / Write memory Modes
• Read data (pattern) from RAM memory and compared
inside comparator to see fail/pass
• ROM Testing:
• Read only Memory
• ROM arrays are tested with a multiple-input signature
register (MISR)
• Contents of the ROM arrays are read for each address,
and then compressed into a signature
• A pre-computed good signature is stored in the MISR and
compared with the resulting signature to determine pass
/ fail status
• Some ROM's store the signature in the most significant
entry in the ROM, but predominantly the signatures are
stored externally

28
 MBIST Operating Modes
•(Contd…)
Programmable BIST (PBIST):

• Programmable MBIST is a mode in which the user can

exercise
own MBIST algorithms on the macros
• By setting controller configuration registers

29
Types of Memory
• SRAM
• TCAM
• ROM
• Multiple ports
• DRAM
• Register file
 SRAM operation

 Idle state : WL =0

 Read : Pre charge BL and BL to 1, then assert WL

if Q = 0, BL will discharge to 0, and BL remains at 1
if Q = 1, BL discharges to 0, and BL remains at 1

 Write : drive BL and BL to the required values and assert WL

 DRAM operation

 Read : Pre charge BL to threshold between logic o and logic 1 and

assert WL. Its a destructive operation.

 Write : Force desired value on BL and assert WL

SMarch Types of Algorithms
SMarchCHKB
SMarchCHKBci
SMarchCHKBcil
SMarchCHKBvcd
ReadOnly
LVMarchX
LVMarchY
LVMarchCMinus
LVMarchLA
LVRowBar
LVColumnBar
LVGalPat
LVGalColumn
LVGalRow
LVCheckerboard1X1
LVCheckerboard4X4
LVWalkingPat
LVBitSurroundDisturb
LVAddressInterconnect
LVDataInterconnect

33
14N: SMarch algorithm
• Sequence :{↓wd} {↓rd, wc} {↑rc, wd, rd, wc} {↑rc, wd}
{↑rd, wc, rc, wd} {↓rd}
• 14N algorithm used for RAM testing
• Takes 14 instructions
• SMarch algorithm is the default test algorithm that the memory BIST
controller uses to test RAMs
• This is the shortest comprehensive test that detects all stuck-at,
transition
and coupling faults etc. for standard RAM's
//Part 0
//{↓ wd} : write data from max address to min address
for (MainAddr=MaxAddrStop; MainAddr>=0; MainAddr--)
wr data @ MainAddr
end
//Part 1
//{↓ rd, wc} : read data from max address to min address, and
replace with compliment data (wc) before changing to next
address.
for (MainAddr=MaxAddrStop; MainAddr>=0; MainAddr--)
rd data @ MainAddr
wr !data @ MainAddr
34
end
14N: SMarch algorithm
(Contd…)
//Part 2
for (MainAddr=0; MainAddr<=MainAddr; MainAddr++)
rd !data @ MainAddr
wr data @ MainAddr
rd data @ MainAddr
wr !data @ MainAddr
end
//Part 3
for (MainAddr=0; MainAddr<=MainAddr; MainAddr++)
rd !data @ MainAddr
wr data @ MainAddr
end
//Part 4
for (MainAddr=0; MainAddr<=MainAddr; MainAddr++)
rd data @ MainAddr
wr !data @ MainAddr
rd !data @ MainAddr
wr data @ MainAddr
end
//Part 5
for (MainAddr=MaxAddrStop; MainAddr>=0; MainAddr--)
rd data @ MainAddr
end 35
Types of Addressing Mode

• Linear

• Fast Column

• Fast Row

• Ping-Pong

• Pseudo-Random Addressing etc.

36
Fast Column / Fast Row
addressing

Mux 0 Mux 1 Mux 0 Mux 1

Fast Column Fast Row

37
Memory Fault Types

•Stuck at 0/1 faults

•Transition faults
•Inversion Coupling Faults
•Dynamic Coupling Faults
•Address Decoder Faults
•Read/Write Logic Faults
•Write Recovery Faults
•Retention Faults
•Parametric Faults

38
Stuck at 0/1 faults
• Memory cell is permanently forced to a logic 0 (stuck-at-0
fault) or logic 1 (stuck-at-1 fault) value ,irrespective of
any value
written to the cell

Step to detect stuck at fault

• SA0 -> read logic 1
• SA1 -> read logic 0

39
Transition faults

• Memory cell fails to undergo a transition from a logic 0 to

a logic 1 value (up transition fault) or from a logic 1 to a
logic 0 value
(down transition fault)

Step to detect an up transition fault

• Cell under test must be storing a logic 0
• Logic 1 must be written into the cell
• Cell must be read before a logic 0 is written to it

40
Inversion Coupling Faults
Fault model, a logic 0 to logic 1 or logic 1 to logic 0
transition in one memory cell (the coupling cell) inverts
the value in another cell (the base cell)

Eg : InCFa: 0 to 1 transition in the coupling cell inverts

the value in the base cell

• Step to detect an InCFa fault

• Coupling cell must be storing a logic 0 and the
value stored in the base cell must be known
• Logic 1 must be written to the coupling cell
• Base cell must be read before any value is written
to it

41
Dynamic Coupling Faults
• Fault model, reading or writing a logic 0 or logic 1 to one
memory cell (the coupling cell) forces the value in another
cell (the base cell) to either a logic 0 or logic 1

Eg : dyCFa: reading or writing a 0 in the coupling cell

forces a 0 in the base cell

• Step to detect dyCFa fault

• The base cell must be storing a logic 1 and the coupling
a logic 0
• The coupling cell must be read or a logic 0 value written
• The base cell must be read before any value is written to

42
 Address Decoder Faults
• This model encompasses faults in the address decoder logic

Eg : Three different faulty behaviors are possible

 ADa: certain address results in no cell being
accessed
 ADb: certain address simultaneously accesses
multiple
cells
 Adc: certain cell can be accessed by multiple
addresses

Step to detect an ADb fault

• Write a logic x to one or more of the cells which are
incorrectly
accessed
• Write a logic x to the effected address 43

• Read from at least one of the cells written to in step 1

Read/Write Logic Faults
 This model encompasses faults in the read/write logic

 Specifically, it covers stuck-at, transition and coupling

(bridging) faults in the write drivers, sense amplifiers, and
data register

 Covering the memory cell array (like stuck-at) faults will

result in covering these faults also

44
Write Recovery Faults
When a value is read from a cell just after the opposite
value has been written to a cell along the same column
and the bit line pre charge has not been performed
correctly

Eg The resulting faulty behaviour is that reading from cell

A just after writing to cell B results in reading the value
written to
cell B

Step to detect a write recovery fault

For a given column address:
• Write a logic x to row address A
• Read a logic xbar from row address B

45
 Retention Faults
Retention fault is one where a cell loses its contents over
time
without being accessed
• Primarily a DRAM cell fault mechanism, resulting from an
abnormally large leakage current

The conditions for optimum detection of a cell retention

fault due
to substrate leakage are as follows
• Write a logic x into the affected cell
• Wait one full refresh cycle (or some arbitrary time
span in the case of an SRAM)
• Read the affected cell

46
 Parametric Faults
• Parametric faults can be classified into DC and AC parametric
faults

• DC parametric faults encompass time independent

voltage/current
abnormalities
- high power consumption
- high current leakage
- high and/or low input voltage thresholds

• AC parametric faults encompass time dependent voltage

abnormalities
- output slow to rise or slow to fall time
- large input setup and hold times
- large output delay times
- large memory cycle times

Applying test patterns at system cycle speeds results in the

detection of the AC parametric faults 47
Algorithms vs Detected faults

48
 MBIST w.r.t.
MentorGraphics

49
• Tool Support :
MBIST Tool to insert MBIST controller ,BIRA, BISR
• Solution
to the design
• Verification of the inserted design using
generated test patterns

• MemoryBIST using LV Flow

50
• Non-Programmable MBIST:
MBIST controllers types
• Provides pre-defined algorithms created for optimized
memory
controller, interfaces size and performance
• Support Hard-coded algorithm (mentor lib algo)

• Programmable MBIST:
• Hard programmable
• Define your own algorithm and design the controller
• Support Hard-coded algorithm

• Soft programmable MBIST:

• Define your own algorithm at the time of testing
• Support Soft-coded and Hard-coded algorithm
+++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++
• Hard-coded algorithm
• User-defined or from the Mentor Graphics library algorithms
• Can't changed after the controller is generated
• Soft-coded algorithm
• User-defined algorithm after memory BIST controller
generation
• Referred to as post-silicon programmable algorithm
51
52
MBIST Controller

53
• BIST_SETUP:i/p:Specifies the run and setup modes for the controller
Signal Port Lists
• MBIST_GO:o/p: Its global pass/fail result from all comparators .During memory failure
occurs, MBIST_GO is driven low and remains low for the duration of memory BIST

• BIST_BIRA_EN:i/p: In redundancy analysis mode

• MBIST_CMP_STAT:o/p: Comparator signal ,if any memory fails, it falls for one cycle and
then rises again

• BIST_DATA_ TO_MEM:o/p:Data to be written to a memory

• MBIST_DIAG_EN :i/p: Input port used for diagnostics

• BIST_SHIFT :i/p: Places the controller in serial shifting (scan) mode, connected to the TAP

• BIST_SI : i/p: Scan input for accessing the controller’s internal registers

• BIST_SO: o/p: Scan output during retrieval of test result and diagnostic data

54
MBIST operating protocol

55
Memory interface for SRAM

56
Memory interface for ROM

57
Memory collar for SRAM

58
Memory collar for ROM

59
 • Comparators can be shared among the sequentially
Types of comparators
tested
memories
• Hence a common CMP_STAT_ID signal can be routed to
chip pins
• Disadvantage is the routing required between
controller and the collar with wide memories

• Comparator within Memory collar:

• Eliminates the routing overhead between collar and
controller
• But its difficult to perform bit-level diagnosis with
single CMP_STAT signal
• Comparator cannot be shared across memories tested

60
Comparators within collar and within controller

61
Diagnostic:
• Bitmapping :
• Bitmapping is used during manufacturing test to assist
process improvement
• Bitmap data is used to guide failure analysis equipment
to the
site of a defect
• On every clock data is shifted out from memory to do
failure
analysis
• This is purely diagnostic or debugging features
• In bitmapping master pauses after every read operation
and transfers the bitmap out of block or design

62
• Tester monitors CMP_STAT_ID from the controller
Compare status output approach
• Capture the Compare Status data at the same rate as the
memory
BIST, controller run and send to chip level pin

63
• Scan based diagnostic approach
Stop-On-Nth-Error
•
approach
Stop the controller when a specified amount errors are
encountered &
Scan out the relevant data for fault diagnosis

• Set “StopOnErrorLimit” property of the ETPlanner

configuration File
to use this

• Eliminates the need to monitor status pins

64
Tessent MemoryBIST Tasks within the LV Flow

65
LV Flow: ETChecker
• Step1 steps

• Step2 : ETPlanner

• Step3 : ETAssemble

• Step4 : ETScan/Pre-Layout ETSignOff

• Step5 : Final ETSignOff

66
LV Flow on RTL level

67
LV Flow on Gate level
Netlist

68
ETChecker

• Check the design for test compliance and fix

any violations.
• Two modes
1) clockInfo
2) ruleCheck
Input Files for ETChecker

• Design Files (RTL or Gate level netlist)

• Cell Library Files
• Memory Library Files
• Pad Library Files
Steps for running ETChecker

• etchecker display –gentemplate ON;

It’ll create display.etchecker,
display.etchecker.README, Makefile
• make display.clockInfo BATCH=on
• make display.ruleCheck BATCH=on
Output Files for ETChecker

• .etCheckerInfo File
• .etpPhysicalInfo File
• .etchecker.rpt_ruleCheck File
 template
• Multiple instances of the same memory should use the same memory template
Memory Lib File
•Memory lib file syntax
MemoryTemplate (<memoryTemplateName>) {
// Begin Memory Template Section
Algorithm: ReadOnly | SMarch |SMarchCHKB | (SMarchCHKBci) |
SMarchCHKBcil | SMarchCHKBvcd | LVMarchX | LVMarchY |
LVAddressInterconnect | LVDataInterconnect |
<algorithmName>;
MemoryType: ROM | (SRAM) | DRAM;
AddressCounter {
Function (Address) {
LogicalAddressMap {
ColumnAddress[x:y] : Address[a:b];
RowAddress[x:y] : Address[a:b];
BankAddress[x:y] : Address[a:b]; } } }
} //End of Memory Template

73
• Extract all design information
ETChecker
• Input files to ETChecker
e.g: *.memlib , other lib file, *.v ,netlist
and .etcScanData
(pre-existing third-party scan chains)

• Run ETChecker to generate configuration file template

$ etchecker <rootModule> \ -genTemplate On

• We will get *.etcheker here : manually EDIT the property

here, based
on your design requirements

• Analyze your RTL and extract clock domain using below

command
• $make <module>.clockInfo -> get from already
generated “<module>.clockInfo” file
or
• $etchecker <rootModule> \ -mode clockInfo \ -
configFile < *.etcheker> \ -memLib <memoryModList> 74
ETChecker
• Verify your design to meets the rules and
requirements(design rules)
• $make <module>.rulecheck
• lv.MemoryInstance property

lv.MemoryInstance -name
<MemoryInstanceName>
-controllerType (NonProgrammable) |
HardProgrammable | SoftProgrammable

• lv.JTAGOption Property to use TAP

lv.JTAGOption -pin <pinName>

[<pinName>]
-option (NJTAG) | DontTouch | CE0 |
CE1 | TDI |TDO | TRST |
TMS | TCK | ANLG| NC |
GND | PWR
-sharedTapPinEnable
-connection <hierarchicalPin>

• Generated output files: “etCheckerInfo &

etpPhysicalInfo” which are required for ETPlanner
75
ETPlanner

• Plan Embedded Test Solution for Entire chip

and generate automated work environment
• Three modes
1) genplan
2) checkplan
3) gen LVWS
Input Files for ETPlanner

• .etCheckerInfo File (Mandatory)

• .memLib Files (Memory Library Files)
• .physicalInfo File
• .LVICTech File
• .ETDefaults File
• .CADsetup File
• DEF or PDEF Files
Steps for running ETPlanner

• etplanner display –mode genplan

It’ll create display.genplan,
display.genplan.README, Makefile
• make checkplan
• make genLVWS
Output Files for ETPlanner

• .etplan File
• .etplan.README File
• Makefile
• .ETSummary File
 affects its embedded test requirements

•ETPlanner
“etpPhysicalInfo” that will list all your memory
instances and assign each of them a clusterID

• “ETDefaults” defines all embedded test defaults for

memory BIST and logic BIST, such as diagnostic
features, power limits, etc.

• When we run with “-mode GenPlan” option,

ETPlanner tool uses the information in the
.etCheckerInfo file and other optional files to
generate an “.etplan” configuration file that
describes the embedded test requirement to plan your
chip

80
ETPlanner (Contd…)
• You can modify .etplan w.r.t. clock domain, controller,
embedded test configuration , memory cluster/group
(instance), algorithm ,BIRA properties (i.e. plan &
specify as per your need)

• Grouping process:
• BIRA Check
• Algorithm Check
• Programmable and Non-Programmable check

• Here “*.etassemble” generated which required for next

flow

81
ETAssembler

• Generate and insert all Embedded Test

Input Files for ETAssembler

• .etassemble Configuration File

• Memory library File
• Design Netlist
• Pad Library File
• Cell Library File
• Pin Order List File
• .lvlib File
Steps for running ETAssembler
• make embedded_test
• make designe
• make synth
• make config_etSignOff
• make concatenated_netlist
• make lvdb_preLayout
• make testbench
• make sim
Output Files for ETAssembler

• Output Netlist
• Log File
• Pin Order List File
• Design Summary File
ETAssemble
• Provide these i/p files to ETAssemble
e.g: *.memlib , *.etassemble, .lvbscan, netlist

• Here MBIST controller hardware and memory interface-collar , e.t.c.

Generated
(Ready !!!)

• Inserted/merged MBIST, LBIST , TAP to your design

• Generates : netlist (with inserted design), etassemble.log, RTL code for

MBIST
controller (cntrl.ext) ,files for the ETAnalysis tools, files for ETVerify,
Diagnostic
bitmapping Interface files

• Now you can run simulation by using “make <test_name>” cmd

86
ETScan/Pre-Layout ETSignOff

•Pre-Layout ETSignOff:
• Perform pre-layout sign-off using rule checkers, Static
timing analysis, and simulations
• Make Targets for Pre-Layout ETSignOff:
• Run the make targets generated by ETPlanner for
Step 4: Pre-Layout to perform pre-layout
embedded test
sign-off using rule checkers, Static timing
analysis, and
simulations

87
Make Targets for Pre-Layout ETSignOff
• The following make targets are found in the ETScan Directory:

• make testbench:
• Generates all testbenches necessary to fully verify each
type and instance of embedded test controllers merged
into your design

• make display_sim_results:
• Shows the summary results of all simulated testbenches

8
8
•Final
SameETSignOff
make targets are used for both Pre-layout ETSignOff
and
Final ETSignOff

• Used to generate the final static timing analysis you use to

sign off
the embedded test timing of your chip

• Final ETSignOff on the final post-layout netlist

• Generate final test vectors, store in LVDB

• Verify these test vectors using any simulator

• Create testcase using “make <test_name>” cmd

• Now run simulation with inserted LBIST design

89
ETVerify
• Use the “MembistPVerify” option to verify your Programmable
controllers

• Multiple below files serve as input to the ETVerify tool:

• *.etv_startup File (clock speed)
• ETVerify Configuration Files (controller config)
• Tessent MemoryBIST Algorithm File(used for soft-coded
algorithms)
• *.controller StepAlgo Selection File (used for soft-coded
algorithms)

• ETVerify could be invoked in the following three steps

• ETAssemble (the ETAssemble directory)
• ETScan and Pre-Layout ETSignOff (the ETScan directory)
• Final ETSignOff (the ETSignOff directory)

90
 Check List

91
Thank You

92
Questions
1. What is number of words ,number of bits in word ,number
of rows ,number of column ,number of words per row in
given figure?
2. Why we require Comparator and how patterns catch
failure on memory?
3. How we do ROM testing ?
4. How many instructions SMarch algorithm takes?
5. What is difference between Fast row and Fast column
addressing modes and who generates this? Mux 0 Mux 1
6. What is transition & Retention faults and how we test it?
7. What are the difference between Programmable and
Soft-Programmable MBIST controller ?
8. Explain MBIST_DONE, MBIST_GO, BIST_BIRA_EN,
MBIST_CMP_STAT signals ?
9. Why we required Diagnostic method ?
10. Define each steps use in LV flow ?
11. In which step of LV flow we do design rule checks ?
12. What are the input files of ETPlanner?
13. In which step of LV flow we do Grouping process?
14. Name the property to configure NonProgrammable,
Programmable, SoftProgrammable bist controller ?
15. In which step of LV flow we use ETVerify and why?
16. Name ETVerify wrapper which we use to verify MBIST ?
93
Answers
1) Number of words = 8 , Number of bits in word = 4,
Number of rows = 4 , Number of column = 8,
ncolmux = Number of words per row = 2

94