ch1 Pub
ch1 Pub
ch1 Pub
&
Assembly
Programming and
Language
系統程式與組合語言
General Introduction
Software
lack of simple definitions
different people give different points of views
relative / operational / . . . definitions
possible definitions :
a group of programs
to complete certain tasks
System Software
System Software v.s. Application Software
System SW v.s. Application SW
are used
directly by system developers
indirectly by end user (consumer)
In This Course (1)
Introduction to
HW :
May be the 1st introduction to computer
architecture
CPU
how to control HW :
Programs
Programming Language
– C : High-level
– Low-level : assembly
programming related system software
In This Course (2)
Practicing : System Software Implementation
we are an engineering department
Loading : Loader
To Get a Program Running
Step 1: Write a Program
Editing : text editor
easy to use, hard to write a one (gui programming)
IDE : Integrated Development Environment
Notepad++ / Eclipse / Dev-C
usually
language A : a high level programming language
– such as C / C++ / Java / . . .
language B : machine code (language)
compiler : high level language translator
C program machine code
program
(source program) (object program)
test.c test.o (test.obj)
Others
OS
Device Drivers
Compiler
Database Management System
In the following
HW : our target machine SIC/XE
Language : its assembly language
translator : assembler
linker
loader
Macro Processor
functions
square-root
sine / cosine / tangent / . . .
logarithm (log), exponential (e)
. . .
good enough ??
why computers?
Calculator v.s. Computer (3)
t1 = b b
t2 = 4 a c
b : key in the number b (4.15933) t =t t
3 1 2
: press time key
b : key in the number b (4.15933) t =t
4 3
t1 = : write down the result in a paper
t = b
5
and mark it as t1
t =t t
6 5 4
t7 = 2 a
t8 = t 6 t7
t9 = t 5 t4
t10 = t9 t7
Calculator v.s. Computer (4)
How about the following situation :
we have 5,000 equations
ai x2 + bi x + ci = 0 i = 1, 2, 3, . . . , 5000
a1=0.134 b1=0.563 c1=3.647 x=?
a2=0.095 b2=0.372 c2=0.215 x=?
. . .
a5000=0.316 b5000=0.814 c5000=0.293 x=?
Differences :
memory !!!!
programs / programming
Calculator v.s.
stepComputer
1 : t = b b (6) 1
step 2 : t2 = 4 a c
Memory
step 3 : t3 = t1 t2
device / component remembers “things”
step 4 : t4 = t3
what are the “things” ??
step 5 : t5 = b
a1, b1, c1, . . . , a5000, step
b5000,6c5000
: t 6 = t5 t 4
t1, t2, t3, . . . step 7 : t7 = 2 a
data step 8 : t8 = t6 t7
step 9 : t9 = t5 t4
step 10: t10 = t9 t7
step1: t1=. . . , step2: t2=. . . , . . . , step
10: . . .
the procedure
programs
1.3 The SIC/XE Machine
SIC Simplified Instructional Computer
simplest version
Instructional : programmable
SIC/XE : SIC XE version
XE : extra equipment
XE : extra expensive
Hypothetic machine (想像的)
simple, concise
almost including everything used in modern
computers
Learning a CPU
Form a programming point of view to learn a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
Learning a CPU
Form a programming point of view to learn a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
Architecture ??
how to build a house??
the common “structure” of all buildings
架梁 (roof beam)
立柱 (pillaring)
舖面 (surfacing)
Top Level : Computer
Peripherals Computer
Central Main
Processing Memory
Unit
Computer Systems
Interconnection
Input
Output
Communication
lines
The CPU
CPU
Computer Arithmetic
and Registers
I/O
Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection bus
Control
Unit
The Control Unit
Control Unit
CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders
Control
Memory
http://www.intel.com/content/www/us/en/intelligent-systems/
embedded-systems-training/ia-introduction-basics-paper.html
Von Neumann Architecture
ALU :
Arithmetic
Logic Unit HDD
TFT LCD
CPU
Registers KeyBoard
memory
i/o & System Mouse
bus
control
CD-ROM
0 1 2 3 . . .
. . .
. . .
Memory Peripherals
Addresses
Learning a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
Memory
bit : high / low ( 0 / 1 )
nibble : 4 bits
byte = 8 bits = 2 nibbles
word : 2 bytes (Intel) 4 bytes (IBM) 3 bytes (SIC)
doubleword = 4 bytes (Intel)
quadword = 8 bytes (Intel)
double quadword = 16 bytes (Intel)
Volatility
volatile : lose power lose contents : DRAM /
SDRAM / DDR-SDRAM
non-volatile : lose power retain contents (EEPROM /
flash memory
Hexadecimal Numbers
binary numbers :
two symbols 0 and 1
examples : 10, 101, 010111001
octal numbers :
8 symbols : 0, 1, 2, 3, 4, 5, 6, 7
examples : 10, 101, 271,
decimal numbers :
10 symbols : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
examples : 10, 101, 185
hexadecimal
16 symbols : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
examples : 10, 101, B9
Number Representation
10, 103, 109, 10A0
binary / Octal / Decimal / Hexadecimal numbers ??
different languages use different ways to represent
in Assembly 101 (
SIC/XE : x'101' 101 (hexadecimal & decimal
only)
Intel :
binary : 101B 101Y
decimal : 101D 101
hexadecimal : 101H 101X
in C : Homework
Why Hexadecimals in
Assembly?
00101100100101000101110101001010
0010 1100 1001 0100 0101 1101 0100
1010
0010 1100 1001 0100 0101 1101 0100
1010
2 C 9 4 5 D 4 A
hexadecimal numbers : 2C945D4A
Hexadecimal Numbers
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal Numbers
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
Hexadecimal Numbers
0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
5 0101 5
6 0110 6
7 0111 7
8 1000 8
9 1001 9
10 1010 A
11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F
Memory
00000 00001 00002 ... FFFFE FFFFF
address
x86 architecture
bit,
byte,
word (2-byte),
double-word (4-byte / 32bit),
quadword (8-byte / 64bit)
double-quadword (16-byte / 128-bit)
SIC Memory
total memory size 32768 (=215 ) Bytes = 32K Bytes
0000 0001 0002 7FFE 7FFF=(32767)10
magic number 15
highest address
(7FFF) 16
= 7FFFX = 7FFFH
= 0x7FFF
=(0111 1111 1111 1111)2
X86 : 232 = 4G Bytes =4GB
X 1 IndeX : 24 bit
for indexed addressing
L 2 Linkage : 24 bit
non-stack equipped machine
used for return address of function call
decode execute
realize the
update PC
instruction :
before entering
How Long
execution stage
PC and Execution Cycle
where is
fetch the instruction?
decode execute
50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61
PC 5A
53
56
PC and Execution Cycle
register PC : where to fetch next instruction
PC 53
then decode : to understand more about the instruction
PC is “updated” right before entering “execute” stage in
execution-cycle
PC 53 My Starting Address
+ 3 My Length
PC 56 Next Instruction Starting Address
50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61
16 bit
AX, BX, CX, DX, DI, SI, BP, SP
32 bit
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP
64 bit
RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP
EAX
AX
RAX
Status Word (Flags) Register
... PF . . . AF ... OF ZF ... SF ... CF ...
1
1 1
+ 0 1
1 0 0
Definition of Flags
most least
significant significant
bit bit
( msb ) ( lsb )
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Definition of Flags
most least
significant significant
bit bit
( msb ) ( lsb )
X23 X22 X21 . . . X2 X1 X0
Definition of Flags
C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z0
partial sum
Definition of Flags
0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Definition of Flags
C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z1 Z0
Definition of Flags
C2 C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z2 Z1 Z0
Definition of Flags
C21 C20 . . . C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z21 . . . Z2 Z1 Z0
Definition of Flags
n-bit : 2n integers
how many for positives and negatives
Signed Integers
n-bit integer (e.g, n = 8)
unsigned : 0 .. 2n-1 (0..255)
signed :
positives : 0 .. 2n-1-1 ( 0 .. 127 )
negatives : -1 .. -2n-1 (-1 .. -128)
2’s complement 01011010
1’s completement 1 0 1 0 0 1 0 1
increment by 1 + 1
10100110
no subtraction for signed numbers :
a–b = a + (– b)
SIC : Data Formats
integers
24-bit
unsigned : 0 .. 16,777,215 (=16M-1)
signed : -8,388,608 .. 8,388,607
2’s complement
characters
8-bit
ASCII code
floating point
not implemented in SIC
Learning a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
Assembly Instruction
Assembly instruction
an instruction is to perform an operation
8 1 15
opcode X addr
instruction
Learning a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SIC : Addressing Mode
single operand instruction :
memory
addressing mode :
representation of memory addressing in machine code
form
8 1 15
opcode x addr
J m 3C 0011 1100 PC m
JEQ m 30 0011 0000 if (ZF == 1) PC m
JGT m 34 0011 0100 if (OF == SF && ZF==0) PC m
JLT m 38 0011 1000 if (OF != SF && ZF==0) PC m
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎
∧
𝟎 𝟎 . . .. 𝟎 𝟏 𝟎 𝟎 𝟎
𝟎 𝟎 . . .. 𝟎 𝒙 𝟑 𝟎 𝟎 𝟎
𝟎 ∧ 𝒙=𝟎 𝟎 ∨ 𝒙= 𝒙
𝟏 ∧ 𝒙=𝒙 𝟏 ∨ 𝒙=𝟏
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎
∨
𝟎 𝟎 . . .. 𝟎 𝟏 𝟎 𝟎 𝟎
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝟏 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎
∨
𝟏 𝟏 .. . . 𝟏𝟎 𝟏 𝟏 𝟏
𝟏 𝟏 .. . . 𝟏 𝒙 𝟑 𝟏 𝟏 𝟏
Learning a CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SIC : Input / Output
transferring 1 byte at a time to/from device
three instructions
TD
WD
RD
TD : test device
TD x’05’
if it is ready for action (read or write)
repeat testing until the device is available (not
busy)
WD : write data (a byte) to device
WD x’05’
write the least significant byte of reg A to
device 0x05
RD : read data (a byte) from device
RD x’0F’
read a byte from device 0x0f and leave it in the
Example 1
alpha RESW 1
five word 5
charZ byte C’Z’
c1 RESB 1
...
LDA five ;load constant 5 into reg. A
STA alpha ;store in alpha
LDCH charZ ;load char ‘Z’ into reg A
STCH c1 ;store in char. variable c1
...
Example 2
one word
1
alpha resw
1
beta resw
1
gamma resw
1
delta resw
1
incr resw
1
. . .
LDA alpha
ADD incr
SUB one
STA beta
LDA
gamma
Example 3
str1 BYTE C’test string’
str2 RESB 11
zero word 0
eleven word 11
. . .
LDX zero
movch LDCH str1,X
STCH str2,X
TIX eleven
JLT movch
. . .
t e s t s t r i n g
str1
, X 2
0
3
1
4
str2
,
t e s t
Example 4
index resw 1
alpha resw 100
beta resw 100
gamma resw 100
zero word 0
K300 word 300
three word 3
LDA zero
STA index
addlp LDX index
LDA alpha, X
ADD beta, X
STA gamma, X
LDA index
ADD three
STA index
COMP K300
JLT addlp
Example 5
indev byte x’F1’
record resb 100
...
zero word 0
JSUB read k100 word 100
...
improvement
more hardware and hence
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Memory
bit, byte, word
byte = 8 bits
1 word = 3 bytes
total memory size 220 = 1024x1024 Bytes = 1M
Bytes
how many bits needed to represent an
address of a locatoion ??
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Registers
all registers in SIC are preserved
A 0 24bit Accumulator
X 1 24bit IndeX
L 2 24bit Linkage
PC 8 24bit Program Counter
SW 9 24bit Status Word
newly added registers
B 3 24bit Base addressing
S 4 24bit general purpose
T 5 24bit general purpose
F 6 48bit Floating point
accumulator
SICXE CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Data Formats
integers
24-bit / 2’s completement
characters
8-bit / ASCII code
floating point
48 bits : 2 words (6 bytes)
1 11 36
s exponent (e) fraction (f )
0 fraction (f ) 1
0 exponent (e) 2047
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Instruction Formats
machine code instruction formats
SIC : single format
8 1 15
opcode X addr
multiple format
opcode : op-tab instruction table in
appendix A
addr : memory address of the operand of
the instruction
SICXE : Instruction Format
8
Format 1 opcode 1 byte
1100 0000
8 4 4
Format 2 opcode r1 2 bytes
r2
1010 1100 0011 0000
6 1 1 1 1 1 1 12
Format 3 3 bytes
opcode n i x b p e disp
0001 10 1 1 1 1 0 0 1010 1110 0011
6 1 1 1 1 1 1 20
Format 4
opcode n i x b p e addr 8-bit
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Addressing Mode (1)
single operand instruction :
register / memory / immediate (constant)
i-bit immediate
6 n i x b p e 12
opcode 1 0 0 disp1
addr = (B) + disp1
disp1 : unsigned number : 0 disp1 < 4096
PC relative mode :
6 n i x b p e 12
opcode 0 1 0 disp2
addr = (PC) + disp2
disp2 : signed number : -2048 disp2 < 2048
SICXE : Addressing Mode (4)
FFFFF FFFFF
PC- Base-
relative relative
data data
next instruction
instruction
instruction
Base
00000 00000
SICXE : Addressing Mode (5)
FFFFF
+2047
2K .. +2K
(2048 .. +2047) +2047
instruction
2048
00001
00000
SICXE : Addressing Mode (6)
E-bit
6 n i x b p e 20
opcode 0 0 1 addr20
TA : Target Address
b, p, e tell us how to get “addr”
(b,p,e) = (1,0,0) addr = (B) + disp12
(b,p,e) = (0,1,0) addr = (PC) + disp12
(b,p,e) = (0,0,1) addr = addr20
(b,p,e) = (0,0,0) addr = disp12
x-bit of instructions in the SIC machine code
direct addressing x = 0 TA = addr
indexed addressingx = 1 TA = addr + (X)
SICXE : Addressing Mode (2)
N- and I-bits
TA : target address is a physical memory location address
n- and i- bits : manage how to use TA
de-referencing operator ( mem-location / register )
n i Description Data
b p e description
0 0 0 immediate value (constant)
1 0 0 format-3 : Base-Relative
0 1 0 format-3 : PC-Relative
0 0 1 format-4 absolute addressing mode
FFFFF
Example
. . .
suppose that 000 000 is the opcode of
0c303 00 30 30 instruction LDA
(B) = 00 60 00h
(PC) = 00 30 00h
06390 00 c3 03 (X) = 00 00 90h
. . .
what are the values of reg. A after executing
each of the following instructions
Hex opcode nixbpe disp
03600 10 30 00
032600 000000 110010 0110 0000 0000
. . . 03c300 10 30
000000 00
111100 0011 0000 0000
022030 00 C3
000000 03
100010 0000 0011 0000
03030 00 36 00
010030 10 30
000000 00
010000 0000 0011 0000
. . . 003600 00 00
000000 30
000011 0110 0000 0000
10 30
0310c303 000000 00
110001
00000 00001100001100000011
00 30 30
Assembly to Machine Code
n i x b p e assembly instruction TA calculation operand
0 1 0 0 0 0 mnemonic #c disp12 TA
0 1 0 0 0 1 +mnemonic #m addr20 TA
integer
example : 8bit 16bit
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Instruction Set (1)
load / store registers
arithmetic operations
logical comparison
conditional / unconditional jumps
subroutine linkage
newly added instructions
multiple formats : 1 - 4
more registers LDB, STB, . . .
floating point arithmetic operations
register-to-register operations : ADDR, SUBR, . . .
privilege instructions : supervisor call SVC . . .
SICXE : Instruction Set (2)
ADD m ¾ 18 0001 1000 A (A) + (m..m+2)
ADDF m ¾ 58 0101 1000 F (F) + (m..m+5)
ADDR r1, r2 2 90 1001 0000 r2 (r2) + (r1)
shift right
Rotate operations
rotate left
rotate right
. . .
register A
shift left operation : SHIFTL A, 1
. . .
. . . ?
0
padding
. . .
. . . 0 0
. . .
?
0 ?
0 . . .
twoways to add
which bit ispaddings
the last moved out bit ??
0 logical right shift
where
arithmetic
is it right
after shift
shifting?
whyarithmetic
kept in CF right(carry
shift ?flag)
keep sign for signed numbers
how to distinguish them?
two different instructions
SHR v.s. SAR
before left shifting : shiftl A, 2
...
if
before shifting right : shiftr A, 3
...
. . .
. . .
CF . . .
𝒙𝟎 CF . . .
J m ¾ 3C 0011 1100 PC := m
JEQ m ¾ 30 0011 0000 if (ZF==1) PC := m
JGT m ¾ 34 0011 0100 if (OF==SF && ZF==0) PC :=
m
JLT m ¾ 38 0011 1000 if (OF!=SF && ZF==0) PC :=
m
Format 3 3 bytes
opcode6 n i x b p e disp12
Format 4 4bytes
opcode6 n i x b p e addr20
SICXE CPU
Architecture
Memory
Registers
Data Formats
Instructional Formats
Addressing Modes
Instruction Set
Input / Output
SICXE : Input / Output
transferring 1 byte at a time to/from a device
TD : test device
if it is ready for action (read or write)
alpha RESW 1
c1 RESB 1
...
LDA #5 load constant 5 into reg. A
STA alpha store in alpha
LDCH #90 load char ‘Z’ into reg A
STCH c1 store in char. variable c1
...
Example 2
one word alpha resw 1
1 beta resw 1
alpha resw gamma resw 1
1
delta resw 1
beta resw
1 incr resw 1
gamma resw . . .
1 LDS incr
delta resw LDA alpha
1
ADDR S,A
incr resw
1 SUB #1
. . . STA beta
LDA alpha LDA
gamma
ADD incr
ADDR S,A
SUB one
SUB #1
S TA beta
STA delta
LDA gamma
ADD incr
Example 3
str1 BYTE C’test str1 BYTE C’test
string’ string’
str2 RESB 11 str2 RESB 11
zero word 0 . . .
eleven word 11 LDT #11
... LDX #0
LDX zero
movch LDCH str1,X
movch LDCH str1,X
STCH str2,X
STCH str2,X
TIX eleven TIXR T
JLT movch JLT movch
... . . .
t e s t s t r i n g
str1
, X 2
0
3
1
4
str2
,
t e s t
Example 4
index resw 1
alpha resw 100 index resw 1
beta resw 100
alpha resw 100
gamma resw 100
zero word 0 beta resw 100
K300 word 300 gamma resw 100
three word 3
LDS #3
LDA zero
LDT #300
STA index
addlp LDX index LDX #0
LDA alpha, X addlp LDA alpha, X
ADD beta, X ADD beta, X
STA gamma, X STA gamma, X
LDA index
ADD three ADDR S, X
STA index COMPR X, T
COMP K300 JLT addlp
JLT addlp
Example 5
indev byte X’F1’
outdev byte X’05’
data RESB 1
. . .
inloop TD indev busy-wait-loop
JEQ inloop
RD indev
STCH data
. . .
outloop TD outdev busy-wait-loop
JEQ outloop
LDCH data
WD outdev
Example 6
JSUB read JSUB read
SunMicro System
workstation
RISC CPU
SunOS (Unix-like)
POWER PC
IBM / Motorola / Apple joint development
RISC