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System Software

&
Assembly
Programming and
Language
系統程式與組合語言
General Introduction
 Software
 lack of simple definitions
 different people give different points of views
 relative / operational / . . . definitions

 possible definitions :
 a group of programs
 to complete certain tasks

 System Software
 System Software v.s. Application Software
System SW v.s. Application SW

 Application Software (Programs)


 Directly support (end-)user’s need
 Examples MS Word / Excel / . . .

 System Software (Programs)


 support other software

 examples : O.S. / Compiler / Assembler / . . .

 are used
 directly by system developers
 indirectly by end user (consumer)
In This Course (1)
 Introduction to
 HW :
 May be the 1st introduction to computer
architecture
 CPU

 how to control HW :
 Programs
 Programming Language
– C : High-level
– Low-level : assembly
 programming related system software
In This Course (2)
 Practicing : System Software Implementation
 we are an engineering department

 we educate students through practicing

 what does “practicing” mean?


 programming
 writing / designing SW (programs) and HW
How To Write a Program?
 Programming Language
 machines designed with only one mother
tongue, i.e., machine code (language)
 for human-being read, write, understand, and
reasoning
 high level programming language : C / C++ /
Java
 工欲善其事 必先利其器

 program = data structure + algorithm (Niklaus


Wirth)

 Software for programming :


 Editor

How to “Get” a
Program Running
 Four Steps
 Selection of programming language (not
much freedom in real world)
 Editing : text editor

 Translation : two types of translators


 high-level languages : compiler
 low-level language : assembler

 Linking : Linkage Editor (Linker)

 Loading : Loader
To Get a Program Running
Step 1: Write a Program
 Editing : text editor
 easy to use, hard to write a one (gui programming)
 IDE : Integrated Development Environment
 Notepad++ / Eclipse / Dev-C

 skip : not to discuss it in this course


To Get a Program Running
Step 2: Translation
 Translator :
 from language A to language B
 A : source language  B : object language
 source program  object program
(source code) (object code)

 usually
 language A : a high level programming language
– such as C / C++ / Java / . . .
 language B : machine code (language)
 compiler : high level language translator
 C program  machine code
program
(source program) (object program)
test.c test.o (test.obj)

 assembler : assembly language translator


 assembly program  machine code
program
(source program) (object program)
test.S test.o (test.obj)
 CPU architecture dependent

 Main problem : forward reference problem


To Get a Program Running
Step 3: Linking
 Linkage Editor (Linker)
 you can not write a program all by yourself

 combine other programs into a “complete”


executable program
 put all related object codes together

 combine your code and previously


translated code (stored in libraries)
 to an executable code (binary / machine
code)
 test.o libc.a  test (test.exe)
 save the executable in a permanent storage
(HDD)

To Get a Program Running
Step 4: Loading
 Loader
 executable version of your program is saved in
a permanent memory (HDD)
 type the command or click an ICON

 copy the program from some permanent


storage, HDD, into main memory (DRAM) for
execution
 copy it into memory, and then execute it

 main problem encountered : relocation


problem
System Software in Your Text
 Programming Tools – how a program get executed
 Language : Assembly Language
 Assembler : Translator
 Linker : How to use other
programs
 Loader : From hard drive to
memory
 Macro Processor :

 Others
 OS
 Device Drivers
 Compiler
 Database Management System
In the following
 HW : our target machine SIC/XE
 Language : its assembly language
 translator : assembler
 linker
 loader
 Macro Processor

use an assembler to assemble


an assembly program
Computer
and
Programming
Calculator v.s. Computer (1)
Calculator v.s. Computer (2)
 what a calculator can do for us?
 arithmetic operations
 addition / subtraction / multiplication / division

 functions
 square-root
 sine / cosine / tangent / . . .
 logarithm (log), exponential (e)
. . .

 good enough ??

 why computers?
Calculator v.s. Computer (3)

 t1 = b  b
 t2 = 4  a  c
b : key in the number b (4.15933) t =t  t 
3 1 2
 : press time key
b : key in the number b (4.15933) t =t  
4 3
t1 = : write down the result in a paper
 t = b 
5
and mark it as t1
 t =t   t 
6 5 4

 t7 = 2  a
 t8 = t 6  t7
 t9 = t 5  t4
 t10 = t9  t7
Calculator v.s. Computer (4)
 How about the following situation :
we have 5,000 equations
ai x2 + bi x + ci = 0 i = 1, 2, 3, . . . , 5000
a1=0.134 b1=0.563 c1=3.647 x=?
a2=0.095 b2=0.372 c2=0.215 x=?
. . .
a5000=0.316 b5000=0.814 c5000=0.293 x=?

 You, experts in IECS department, how to solve this


problem, ?
 Computer !!!
 Why / How ? Write a program !!!
Calculator v.s. Computer (5)
 Similarities
 arithmetic operations :
 addition / subtraction / multiplication / division
 integer / floating point

 “functions” : sin, cos, log, exp, . . .

 Differences :
 memory !!!!

 much more complicate “controls”

 programs / programming
Calculator v.s.
stepComputer
1 : t = b  b (6) 1

step 2 : t2 = 4  a  c
 Memory
step 3 : t3 = t1  t2
 device / component remembers “things”
step 4 : t4 = t3 
 what are the “things” ??
step 5 : t5 = b 
 a1, b1, c1, . . . , a5000, step
b5000,6c5000
: t 6 = t5   t 4 
 t1, t2, t3, . . . step 7 : t7 = 2  a
 data step 8 : t8 = t6  t7
step 9 : t9 = t5  t4

step 10: t10 = t9  t7
step1: t1=. . . , step2: t2=. . . , . . . , step
10: . . .
 the procedure
 programs
1.3 The SIC/XE Machine
 SIC Simplified Instructional Computer
 simplest version
 Instructional : programmable
 SIC/XE : SIC XE version
 XE : extra equipment
 XE : extra expensive
 Hypothetic machine (想像的)
 simple, concise
 almost including everything used in modern
computers
Learning a CPU
Form a programming point of view to learn a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
Learning a CPU
Form a programming point of view to learn a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
Architecture ??
 how to build a house??
 the common “structure” of all buildings

架梁 (roof beam)

立柱 (pillaring)

舖面 (surfacing)
Top Level : Computer

Peripherals Computer

Central Main
Processing Memory
Unit
Computer Systems
Interconnection

Input
Output
Communication
lines
The CPU

CPU

Computer Arithmetic
and Registers
I/O
Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection bus

Control
Unit
The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
http://www.intel.com/content/www/us/en/intelligent-systems/
embedded-systems-training/ia-introduction-basics-paper.html
Von Neumann Architecture
ALU :
Arithmetic
Logic Unit HDD
TFT LCD
CPU
Registers KeyBoard
memory
i/o & System Mouse
bus
control
CD-ROM
0 1 2 3 . . .
. . .
. . .
Memory Peripherals
Addresses
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
Memory
 bit : high / low ( 0 / 1 )
 nibble : 4 bits
 byte = 8 bits = 2 nibbles
 word : 2 bytes (Intel) 4 bytes (IBM) 3 bytes (SIC)
 doubleword = 4 bytes (Intel)
 quadword = 8 bytes (Intel)
 double quadword = 16 bytes (Intel)
 Volatility
 volatile : lose power  lose contents : DRAM /
SDRAM / DDR-SDRAM
 non-volatile : lose power retain contents (EEPROM /
flash memory
Hexadecimal Numbers
 binary numbers :
 two symbols 0 and 1
 examples : 10, 101, 010111001
 octal numbers :
 8 symbols : 0, 1, 2, 3, 4, 5, 6, 7
 examples : 10, 101, 271,
 decimal numbers :
 10 symbols : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
 examples : 10, 101, 185
 hexadecimal
 16 symbols : 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
 examples : 10, 101, B9
Number Representation
10, 103, 109, 10A0
 binary / Octal / Decimal / Hexadecimal numbers ??
 different languages use different ways to represent
 in Assembly 101 (
 SIC/XE : x'101' 101 (hexadecimal & decimal
only)
 Intel :
 binary : 101B 101Y
 decimal : 101D 101
 hexadecimal : 101H 101X

 in C : Homework
Why Hexadecimals in
Assembly?
00101100100101000101110101001010
0010 1100 1001 0100 0101 1101 0100
1010
0010 1100 1001 0100 0101 1101 0100
1010
2 C 9 4 5 D 4 A
 hexadecimal numbers : 2C945D4A
Hexadecimal Numbers
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal Numbers
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
Hexadecimal Numbers
0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
5 0101 5
6 0110 6
7 0111 7
8 1000 8
9 1001 9
10 1010 A
11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F
Memory
00000 00001 00002 ... FFFFE FFFFF

 what are numbers 00000, 00001, 00002, . . . ,


FFFFF
 addresses
 where the data stored

 the number given by architecture for each “cell”

 cell : byte / word


 byte-addressable / word-addressable

 address

 1-bit address : can number 2 cells


 2-bit address : can number 4 cells

 n-bit address  2n addresses : total memory


SIC Memory
 units : bit, byte, word
 byte = 8 bits

 1 word = 3 bytes = 24 bits

 x86 architecture
 bit,
 byte,
 word (2-byte),
 double-word (4-byte / 32bit),
 quadword (8-byte / 64bit)
 double-quadword (16-byte / 128-bit)
SIC Memory
 total memory size 32768 (=215 ) Bytes = 32K Bytes
0000 0001 0002 7FFE 7FFF=(32767)10

 magic number 15

 highest address
(7FFF) 16

= 7FFFX = 7FFFH
= 0x7FFF
=(0111 1111 1111 1111)2
 X86 : 232 = 4G Bytes =4GB

 what is the highest address : 232-1


Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
Registers
 memory inside CPU
 used for
 computing : in/out data temporary storage
operations such as addition/subtraction/. . .
 system control : function setting

 system status : hardware


SIC : Registers
 A 0 Accumulator : 24 bit
arithmetical operation default operand
EAX (AX, AL) in x86 architecture

 X 1 IndeX : 24 bit
for indexed addressing

 L 2 Linkage : 24 bit
non-stack equipped machine
used for return address of function call

 PC 8 program counter : 24 bit (CS,EIP in x86 )

 SW 9 Status Word : 24 bit (System Flags,


EFLAGS in x86 )
PC : Program Counter
 The program counter ( PC ), also called the
 instruction pointer, or
 instruction address register, or
 instruction sequencer

is a processor register that indicates where the computer is in


its instruction sequence.
 Depending on the details of the particular computer, the PC
holds either
 the address of the instruction being executed, or

 the address of the next instruction to be


executed. (applied in SIC and SICXE)
Execution Cycle and PC
 CPU :
 execute instructions (one-by-one)
 circular routine job
What To Do
read next • read operands
instruction from • execute operation
memory: fetch • write result
Where

decode execute

realize the
update PC
instruction :
before entering
How Long
execution stage
PC and Execution Cycle
where is
fetch the instruction?

decode execute

50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61

blue orange green


instruction instruction instruction

PC 5A
53
56
PC and Execution Cycle
 register PC : where to fetch next instruction
PC 53
 then decode : to understand more about the instruction
 PC is “updated” right before entering “execute” stage in
execution-cycle
PC 53 My Starting Address
+ 3 My Length
PC 56 Next Instruction Starting Address

50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61

 when executing the blue instruction


orange
blue instruction instruction PC points to the orange
instruction
 As long as we have the address of the “current”
being executed instruction
then we know (can compute) where (the address of)
the next instruction to be executed is
 Problem :
How do we know the address of the 1st instruction?
 It can NOT be computed
 we need other “person” (program) to tell us (set an
address) to PC
General Purpose Registers
in X86
 8 bit
 AH, AL , BH, BL , CH, CL , DH, DL

 16 bit
 AX, BX, CX, DX, DI, SI, BP, SP
 32 bit
 EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP
 64 bit
 RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP
EAX
AX
RAX
Status Word (Flags) Register
... PF . . . AF ... OF ZF ... SF ... CF ...

 results related to arithmetic operations


 used as result of comparison
 commonly used in all machines
 carry flag CF
 Sign flag SF
 Zero flag ZF
 Overflow flag OF
 X86 architecture has two more
 Auxiliary flagAF
 Parity flag PF
Carry
5
+ 8
13
1 1
5 5 05
+ 8 + 8 + 08
3 13
1 1 0
68 68 068 068
+ 147 + 147 + 147 + 147
5 215 215
1-bit adder
0 0 1 1
+ 0 + 1 + 0 + 1
0 1 1 10
Carry bit

1
1 1
+ 0 1
1 0 0
Definition of Flags
most least
significant significant
bit bit
( msb ) ( lsb )
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Definition of Flags
most least
significant significant
bit bit
( msb ) ( lsb )
X23 X22 X21 . . . X2 X1 X0
Definition of Flags

X23 X22 X21 . . . X2 X1 X0


+ y23 Y22 Y21 . . . Y2 Y1 Y0

24 bit integer + 24 bit integer


Definition of Flags
carry bit

C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z0

partial sum
Definition of Flags

0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Definition of Flags

C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z1 Z0
Definition of Flags

C2 C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z2 Z1 Z0
Definition of Flags

C21 C20 . . . C1 C0 0
X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z21 . . . Z2 Z1 Z0
Definition of Flags

C22 C21 C20 . . . C1 C0 0


X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z22 Z21 . . . Z2 Z1 Z0
Definition of Flags

C23 C22 C21 C20 . . . C1 C0 0


X23 X22 X21 . . . X2 X1 X0
+ y23 Y22 Y21 . . . Y2 Y1 Y0
Z23 Z22 Z21 . . . Z2 Z1 Z0
Definition of Flags
C23 C22 C21 C20 ... C1 C0 0
X23 X22 X21 X2 X1 X0
+ y23 Y22 Y21 Y2 Y1 Y0
Z23 Z22 Z21 Z2 Z1 Z0
most significant bit unsigned integerleast
overflow flagbit
significant
(msb) for
CFsigned integer(lsb)
= 1 overflow occurred
SF = 1 the result is negative ( <0 )
Carry flag for
CF = CSFresult is zero ??
= 0 the result is positive (>=0)
ZF =231 the result is zero ( = 0 )
Sign flag SF =
ZFZinteger
signed =230 the overflow
result is non-zero
flag (0)
Zero flag OF ==1 ~
ZF overflow
(Z23 | Zoccurred
22 | . . . | Z1 | Z0)

Overflow flag OF = C23⊕ C22


Comparisons
 x?y x–y ? 0
x = y  x–y = 0
x  y  x–y  0
x  y  x–y  0
x  y  x–y  0
x  y  x–y  0
x  y  x–y  0
Comparison and Flags
 compare x and y
 x y
 flags changed
 e.g., ZF = 1
 if and only if x  y  0
 this means x  y

 “EQ”ual  ZERO (ZF=1)


Comparison and Flags
 signed integer comparison
 GT (Greater Than) : OF = SF && ZF=0
 GE (Greater than or Equal to) : OF = SF || ZF = 1
 LT (Less Than) : OF != SF && ZF = 0
 LE (Less than or Equal to) : OF != SF || ZF
=1

 unsigned integer comparison


 GT (Greater Than) : CF=0 && ZF=0
 GE (Greater than or Equal to) : CF=0 || ZF = 1
 LT (Less Than) : CF=1 && ZF = 0
 LE (Less than or Equal to) : CF=1 || ZF = 1
X86 Conditional Jumps
cmp x ; do A-x
 signed integer comparison
 gt : if OF == SF && ZF == 0
 ge : if OF == SF || ZF == 1
 lt : if OF != SF && ZF == 0
 le : if OF != SF || ZF == 1
 unsigned integer comparison
 ja : if CF == 0 && ZF == 0
 ae : if CF == 0 || ZF == 1
 jb : if CF == 1 && ZF == 0
 jbe : if CF == 1 || ZF == 1
 signed and unsigned
 jeq : if ZF == 1
 jne : if ZF == 0
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
2’s Completement
16-bit integer
1 1 0 1 0 0 1 1 1 0 1 0 0 1 0 0
+ 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 1
+ 1 1 1 1 1
Its 11’s 1complement
1 1 1 1 1 1 1 1 1
1 0 0 1 0 0 0 0 1
+ 0 0 1 0 1
0  1 0 0 0
1 0
1 0
1 0 1
0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1  0
2’s complement
of the 16-bit integer
1101 0011 1010 0100
2’s Completement
16-bit integer
1 1 0 1 0 0 1 1 1 0 1 0 0 1 0 0
+ 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 1
1 1 1 1 1
Its 11’s 1complement
1 1 1 1 1 1 1 1 1
+ 1
0  1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1  0
0 0 00 0 0 0000
1 0 00 0 1 01
1 01 01
2 0 00 1 0 01 01 1 10
3 0 00 1 1 0 01
1 01 0 00
1 01
4 0 11 0 0 1 11 11 10 10
5 0 11 0 1 1 1 1 1 01
6 0 11 1 0 11101
7 0 11 1 1
-8
? 1 00 0 0
-7
? 1 00 0 1
-6
? 1 00 1 0
-5
? 1 00 1 1
-4
? 1 11 0 0
-3
? 1 11 0 1
-2
? 1 11 1 0
-1
? 1 11 1 1
Negatives
 4-bit : 24 (=16) integers
 24 / 2 = 8 : positives :0, 1, 2, 3, 4, 5, 6, 7
 24 / 2 = 8 : negatives : -1,-2,-3,-4,-5,-
6,-7,-8
 no +8

 8-bit : 28 (=256) integers


 28 / 2 = 128 : positives : 0, 1, 2, . . . ,
127
 28 / 2 = 128 : negatives : -1, -2, . . . , -
127, -128
 no +128

 n-bit : 2n integers
 how many for positives and negatives
Signed Integers
 n-bit integer (e.g, n = 8)
 unsigned : 0 .. 2n-1 (0..255)
 signed :
 positives : 0 .. 2n-1-1 ( 0 .. 127 )
 negatives : -1 .. -2n-1 (-1 .. -128)
 2’s complement 01011010
 1’s completement 1 0 1 0 0 1 0 1
 increment by 1 + 1
10100110
 no subtraction for signed numbers :
a–b = a + (– b)
SIC : Data Formats
 integers
 24-bit
 unsigned : 0 .. 16,777,215 (=16M-1)
 signed : -8,388,608 .. 8,388,607
 2’s complement

 characters
 8-bit
 ASCII code

 floating point
 not implemented in SIC
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
Assembly Instruction
 Assembly instruction
 an instruction is to perform an operation

 operations : addition, subtraction, . . .


LDA : + –alpha
 operator × ÷
ADD : 23
 operands INCR
+ x
– SUB
unary - one
b
– STA
binary a beta
+ b
– trinary a ? b : c
LDA :
 notation gamma
– ADD INCR: a + b
infix notation
– SUB one
prefix notation : + a, b
– STA
mnemonic Delta : add a, b
SIC : Instruction Formats
 machine code instruction single format

8 1 15
opcode X addr

1011 0110 1 001 1011 1001 0100


0010 1010 0 010 0010 1100 0001

 opcode : op-tab instruction table in appendix A

 addr : memory address of the operand of the

instruction
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
SIC : Addressing Mode
 single operand instruction :
 memory

 addressing mode :
 representation of memory addressing in machine code
form
8 1 15
opcode x addr

 addr : third field of instructions in SIC machine code


 target address (TA) : memory location address
 x-bit of instructions in the SIC machine code
 direct addressing x = 0 TA = addr
 indexed addressing x = 1 TA = addr + (X)
 (X) content of register X (dereferencing operator)
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
SIC : Instruction Set
 load / store registers
 LDA / STA / LDX / STX
 Load / Read / Get : memory  CPU (register)
 Store / Write / Put : CPU (register)  memory
 arithmetic operations
 ADD (addition + ) / SUB (subtraction  ) / MUL
(multiplication ) / DIV (division  )
 logical opertions
 CMP (comparison ? )
 conditional jump
 J / JGT / JLT / JEQ
 subroutine linkage
 JSUB (call) / RSUB (return)
SIC : Instruction Set (1)
ADD m 18 0001 1000 A  (A) + (m..m+2)
SUB m 1C 0001 1100 A  (A)  (m..m+2)
MUL m 20 0010 0000 A  (A) * (m..m+2)
DIV m 24 0010 0100 A  (A) / (m..m+2)

AND m 40 0100 0000 A  (A) & (m..m+2)


OR m 44 0100 0100 A  (A) | (m..m+2)

J m 3C 0011 1100 PC  m
JEQ m 30 0011 0000 if (ZF == 1) PC  m
JGT m 34 0011 0100 if (OF == SF && ZF==0) PC  m
JLT m 38 0011 1000 if (OF != SF && ZF==0) PC  m

JSUB m 48 0100 1000 L  (PC) ; PC  m


RSUB 4C 0100 1100 PC  (L)
SIC : Instruction Set (2)
LDA m 00 0000 0000 A  (m..m+2)
LDCH m 50 0101 0000 A[l.s.b]  (m)
LDX m 04 1001 0100 X  (m..m+2)
LDL m 08 0000 1000 L  (m..m+2)

STA m 0C 0000 1100 m..m+2  (A)


STCH m 54 0101 0000 m  A[l.s.b]
STX m 10 1001 0100 m..m+2  (X)
STL m 14 0001 0100 m..m+2  (L)

COMP m 2B 0010 1101 (A) ? (m..m+2)

TIX m 2C 0010 1100 X(X)+1; (X)?(m..m+2)

TD m E0 1110 0000 test if device m busy


RD m D8 1101 1000 read from device m
WD m DC 1101 1100 write to device m
𝒙=𝟎
𝟎 ∧ 𝒙=? 𝒙= 𝒙
𝟎 ∨ 𝒙=?
𝟏 ∧ 𝒙=?
𝒙=𝒙 𝟏 ∨ 𝒙=?
𝒙=𝟏
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝟏 𝟏 .. . . 𝟏𝟎 𝟏 𝟏 𝟏
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝟎 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝟎 𝟎 . . .. 𝟎 𝟏 𝟎 𝟎 𝟎
𝟎 𝟎 . . .. 𝟎 𝒙 𝟑 𝟎 𝟎 𝟎
𝟎 ∧ 𝒙=𝟎 𝟎 ∨ 𝒙= 𝒙
𝟏 ∧ 𝒙=𝒙 𝟏 ∨ 𝒙=𝟏

𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝟎 𝟎 . . .. 𝟎 𝟏 𝟎 𝟎 𝟎
𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝟏 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝒙 𝟐𝟑 𝒙 𝟐𝟐 .. . . 𝒙 𝟒 𝒙 𝟑 𝒙 𝟐 𝒙 𝟏 𝒙 𝟎

𝟏 𝟏 .. . . 𝟏𝟎 𝟏 𝟏 𝟏
𝟏 𝟏 .. . . 𝟏 𝒙 𝟑 𝟏 𝟏 𝟏
Learning a CPU
 Architecture
 Memory
 Registers
 Data Formats
 Instructional Formats
 Addressing Modes
 Instruction Set
 Input / Output
SIC : Input / Output
 transferring 1 byte at a time to/from device
 three instructions
 TD

 WD

 RD
 TD : test device
 TD x’05’
 if it is ready for action (read or write)
 repeat testing until the device is available (not
busy)
 WD : write data (a byte) to device
 WD x’05’
 write the least significant byte of reg A to
device 0x05
 RD : read data (a byte) from device
 RD x’0F’
 read a byte from device 0x0f and leave it in the
Example 1
alpha RESW 1
five word 5
charZ byte C’Z’
c1 RESB 1
...
LDA five ;load constant 5 into reg. A
STA alpha ;store in alpha
LDCH charZ ;load char ‘Z’ into reg A
STCH c1 ;store in char. variable c1
...
Example 2
one word
1
alpha resw
1
beta resw
1
gamma resw
1
delta resw
1
incr resw
1
. . .
LDA alpha
ADD incr
SUB one
STA beta

LDA
gamma
Example 3
str1 BYTE C’test string’
str2 RESB 11
zero word 0
eleven word 11
. . .
LDX zero
movch LDCH str1,X
STCH str2,X
TIX eleven
JLT movch
. . .

t e s t s t r i n g

str1
, X 2
0
3
1
4
str2
,
t e s t
Example 4
index resw 1
alpha resw 100
beta resw 100
gamma resw 100
zero word 0
K300 word 300
three word 3

LDA zero
STA index
addlp LDX index
LDA alpha, X
ADD beta, X
STA gamma, X
LDA index
ADD three
STA index
COMP K300
JLT addlp
Example 5
indev byte x’F1’
record resb 100
...
zero word 0
JSUB read k100 word 100
...

read LDX zero


rloop TD indev
JEQ rloop
RD indev
STCH record, X
TIX k100
JLT rloop
RSUB
SIC  SIC/XE
 SIC too simple to be practical

 improvement
 more hardware and hence

 much more complicate control

 SICXE is backward compatible with SIC


 SICXE contains most features of today’s CPU
designs
SICXE CPU
Form a programming point of view to learn a CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Memory
 bit, byte, word
 byte = 8 bits

 1 word = 3 bytes
 total memory size 220 = 1024x1024 Bytes = 1M
Bytes
 how many bits needed to represent an

address of a locatoion ??

00000 00001 00002 FFFFE FFFFF


SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Registers
 all registers in SIC are preserved
A 0 24bit Accumulator
X 1 24bit IndeX
L 2 24bit Linkage
 PC 8 24bit Program Counter
 SW 9 24bit Status Word
 newly added registers
B 3 24bit Base addressing
S 4 24bit general purpose
T 5 24bit general purpose
F 6 48bit Floating point
accumulator
SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Data Formats
 integers
 24-bit / 2’s completement
 characters
 8-bit / ASCII code
 floating point
 48 bits : 2 words (6 bytes)

1 11 36
s exponent (e) fraction (f )

 0  fraction (f )  1
 0  exponent (e)  2047

 stored value is : (-1)sf2 (e-1024)


SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Instruction Formats
 machine code instruction formats
 SIC : single format

8 1 15
opcode X addr

 multiple format
 opcode : op-tab instruction table in
appendix A
 addr : memory address of the operand of
the instruction
SICXE : Instruction Format
8
Format 1 opcode 1 byte
1100 0000
8 4 4
Format 2 opcode r1 2 bytes
r2
1010 1100 0011 0000

6 1 1 1 1 1 1 12
Format 3 3 bytes
opcode n i x b p e disp
0001 10 1 1 1 1 0 0 1010 1110 0011

6 1 1 1 1 1 1 20
Format 4
opcode n i x b p e addr 8-bit

0001 10 0 1 1 0 0 1 1010 1110 0011 1011 1101


4 bytes
SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Addressing Mode (1)
 single operand instruction :
 register / memory / immediate (constant)

 representation of memory addressing in machine code


form
 addressing mode n, i, x, b, p, e bits:
 n-bit : indirect

 i-bit immediate

 x-bit of instructions in the SIC machine code


 direct addressing x = 0 TA = addr
 indexed addressing x = 1 TA = addr + (X)
 b-bit base-relative mode mutual exclusive
 p-bit PC-relative mode at most one of them
 e-bit extension bit  format 4 can be set (1)
SICXE : Addressing Mode (3)
B-, and P-bit
Relative Addressing mode
 format 3 :
 Base relative mode :

6 n i x b p e 12
opcode 1 0 0 disp1
 addr = (B) + disp1
 disp1 : unsigned number : 0  disp1 < 4096
 PC relative mode :

6 n i x b p e 12
opcode 0 1 0 disp2
 addr = (PC) + disp2
 disp2 : signed number : -2048  disp2 < 2048
SICXE : Addressing Mode (4)
FFFFF FFFFF
PC- Base-
relative relative
data data

PC-relative disp Base-relative disp


(-2048 .. 2047) ( 0 .. 4095 )

next instruction
instruction
instruction

Base
00000 00000
SICXE : Addressing Mode (5)
FFFFF

+2047

PC-relative mode instruction


data accessible
range 2048

2K .. +2K
(2048 .. +2047) +2047

instruction

2048
00001
00000
SICXE : Addressing Mode (6)
E-bit

format 4 : an extension of format 3

 format 4 : absolute addressing mode


 addr : 20 bits of physical address
 no more adjustment will be take except +(X)

6 n i x b p e 20

opcode 0 0 1 addr20
TA : Target Address
 b, p, e tell us how to get “addr”
 (b,p,e) = (1,0,0) addr = (B) + disp12
 (b,p,e) = (0,1,0) addr = (PC) + disp12
 (b,p,e) = (0,0,1) addr = addr20
 (b,p,e) = (0,0,0) addr = disp12
 x-bit of instructions in the SIC machine code
 direct addressing x = 0 TA = addr
 indexed addressingx = 1 TA = addr + (X)
SICXE : Addressing Mode (2)
N- and I-bits
 TA : target address is a physical memory location address
 n- and i- bits : manage how to use TA
 de-referencing operator ( mem-location / register )

 get the value stored in mem-location / register

n i Description Data

0 0 SIC addressing mode (TA)


1 1 SICXE simple (normal) (TA)
1 0 SICXE indirect mode ((TA))
0 1 SICXE immediate mode TA
SICXE : Addressing Mode (7)
How to choose addressing mode
 programmer (assembly language) level
 programmers choose format 3 or 4
 why format 3 (relative mode)
 save memory size (12 bits v.s. 20 bits)
 relocation
 why format 4 (absolute mode)
 limited range size for displacement in format-3

 assembler (machine code) level


 assembler chooses B-rel or PC-rel modes
 Base-rel ( (B) .. (B)+4095 )
 PC-rel ( next.Inst.Loc.-2048 .. next.Inst.Loc.+2047 )
SICXE : Addressing Mode (8)
 assembler generate information for machine code

b p e description
0 0 0 immediate value (constant)
1 0 0 format-3 : Base-Relative
0 1 0 format-3 : PC-Relative
0 0 1 format-4 absolute addressing mode
FFFFF
Example
. . .
suppose that 000 000 is the opcode of
0c303 00 30 30 instruction LDA
(B) = 00 60 00h
(PC) = 00 30 00h
06390 00 c3 03 (X) = 00 00 90h

. . .
what are the values of reg. A after executing
each of the following instructions
Hex opcode nixbpe disp
03600 10 30 00
032600 000000 110010 0110 0000 0000
. . . 03c300 10 30
000000 00
111100 0011 0000 0000
022030 00 C3
000000 03
100010 0000 0011 0000
03030 00 36 00
010030 10 30
000000 00
010000 0000 0011 0000
. . . 003600 00 00
000000 30
000011 0110 0000 0000
10 30
0310c303 000000 00
110001
00000 00001100001100000011
00 30 30
Assembly to Machine Code
n i x b p e assembly instruction TA calculation operand

0 0 0 - - - mnemonic m b/p/e/disp 15 bits (TA)

0 0 1 - - - mnemonic m, X b/p/e/disp 15 bits+(X) (TA)

1 1 0 0 0 0 mnemonic c disp12 (TA)

1 1 0 0 0 1 +mnemonic m addr (TA)

1 1 0 0 1 0 mnemonic m (PC)+ disp12 (TA)

1 1 0 1 0 0 mnemonic m (B) + disp12 (TA)

1 1 1 0 0 0 mnemonic c , X disp12 +(X) (TA)

1 1 1 0 0 1 +mnemonic m , X addr20 +(X) (TA)

1 1 1 0 1 0 mnemonic m , X (PC)+ disp12 +(X) (TA)

1 1 1 1 0 0 mnemonic m , X (B) + disp12 +(X) (TA)


Assembly to Machine Code
(2)
 indirect

n i x b p e assembly instruction TA calculation operand

1 0 0 0 0 0 mnemonic @c disp12 ((TA))

1 0 0 0 0 1 +mnemonic @m addr 20 ((TA))

1 0 0 0 1 0 mnemonic @m (PC)+ disp12 ((TA))


1 0 0 1 0 0 mnemonic @m (B) + disp12 ((TA))
 immediate

n i x b p e assembly instruction TA calculation operand

0 1 0 0 0 0 mnemonic #c disp12 TA

0 1 0 0 0 1 +mnemonic #m addr20 TA

0 1 0 0 1 0 mnemonic #m (PC)+ disp12 TA


0 1 0 1 0 0 mnemonic #m (B) + disp12 TA
Signed / Zero Extension
 number of bits (size) used to represent an integer
 8 bits : char

 16 bits : short int

 32 bits : long int

 64 bits : longlong int

 size change : small size  large size : perfectly OK


 8bit  16bit  32bit  64bit
 16bit  32bit  64bit
 32bit  64bit

 large size  small size : very likely to be erroneous


 unsigned integer : zero extension
 always “pad” zeros
 example : 8bit  16bit
0010 1010  0000 0000 0010 1010
1011 0110  0000 0000 1011 0110
 signed integer : signed extension
 “pad” according to value of the sign bit of the

integer
 example : 8bit  16bit

0010 1010  0000 0000 0010 1010


1011 0110  1111 1111 1011 0110
opcode nixbpe disp
022030 000000 100010 0000 0011
 PC =0000
0x003456, disp = 0x030, x-bit = 0
 TA = 0x003456
+ 0x000030
0x 030
0x003486

opcode nixbpe disp


022030 000000 100010 1100 0011
 PC = 0x003456, disp = 0xC30, x-bit = 0
0000
 TA = 0x003456
+ 0x
0xFFFC30
C30
0x003086
SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Instruction Set (1)
 load / store registers
 arithmetic operations
 logical comparison
 conditional / unconditional jumps
 subroutine linkage
newly added instructions
 multiple formats : 1 - 4
 more registers LDB, STB, . . .
 floating point arithmetic operations
 register-to-register operations : ADDR, SUBR, . . .
 privilege instructions : supervisor call SVC . . .
SICXE : Instruction Set (2)
ADD m ¾ 18 0001 1000 A  (A) + (m..m+2)
ADDF m ¾ 58 0101 1000 F  (F) + (m..m+5)
ADDR r1, r2 2 90 1001 0000 r2  (r2) + (r1)

SUB m ¾ 1C 0001 1100 A  (A)  (m..m+2)


SUBF m ¾ 5C 0101 1100 F  (F)  (m..m+5)
SUBR r1, r2 2 94 1001 0100 r2  (r2)  (r1)

MUL m ¾ 20 0010 0000 A  (A) * (m..m+2)


MULF m ¾ 60 0110 0000 F  (F) * (m..m+5)
MULR r1, r2 2 98 1001 1000 r2  (r2) * (r1)

DIV m ¾ 24 0010 0100 A  (A) / (m..m+2)


DIVF m ¾ 64 0110 0100 F  (F) / (m..m+5)
DIVR r1, r2 2 9C 1001 1100 r2  (r2) / (r1)

AND m ¾ 40 0100 0000 A  (A) & (m..m+2)


OR m ¾ 44 0100 0100 A  (A) | (m..m+2)
SICXE : Instruction Set (3)
LDA m ¾ 00 0000 0000 A  (m..m+2)
LDB m ¾ 68 0110 1000 B  (m..m+2)
LDCH m ¾ 50 0101 0000 A[l.s.b]  (m)
LDF m ¾ 70 0111 0000 F  (m..m+5)
LDL m ¾ 08 0000 1000 L  (m..m+2)
LDS m ¾ 6C 0110 1100 S  (m..m+2)
LDT m ¾ 74 0111 0100 T  (m..m+2)
LDX m ¾ 04 0000 0100 X  (m..m+2)
STA m ¾ 0C 0000 1100 m..m+2  (A)
STB m ¾ 78 0111 1000 m..m+2  (B)
STCH m ¾ 54 0101 0100 m  (A[l.s.b])
STF m ¾ 80 1000 0000 m..m+5  (F)
STI m ¾ D4 1101 0100 timer  (m..m+2)
STL m ¾ 14 0001 0100 m..m+2  (L)
STS m ¾ E8 1110 1000 m..m+2  (S)
STT m ¾ 84 1000 0100 m..m+2  (T)
STX m ¾ 10 0001 0000 m..m+2  (X)
LPS m ¾ D0 1101 0000 SW  (m..m+2)
STSW m ¾ E8 1110 1000 m..m+2  (SW)
SHIFT Operations
 Shift operations
 shift left

 shift right

 Rotate operations
 rotate left

 rotate right
. . .
register A
 shift left operation : SHIFTL A, 1

. . .

. . . ?
0

padding

where is (the last moved out bit) after shifting ?


answer : kept in CF (carry flag)
Shift Left
 shift left operation : SHIFTL A, 2

. . .

. . . 0 0

• which is the last moved out bit ??


paddings
• where is it after shifting?
• kept in CF (carry flag)
Shift Right
 shift right operation : SHIFTR A, 2

. . .

?
0 ?
0 . . .

twoways to add
which bit ispaddings
the last moved out bit ??
 0 logical right shift
  where
arithmetic
is it right
after shift
shifting?
whyarithmetic
kept in CF right(carry
shift ?flag)
 keep sign for signed numbers
how to distinguish them?
 two different instructions
 SHR v.s. SAR
 before left shifting : shiftl A, 2
...

 after shifting : shiftl A, 2


. . .

if
 before shifting right : shiftr A, 3
...

after shifting : shiftr A, 3


0 0 . . .
shiftness v.s. arithmetics
 right shift position divided by
 SIC/XE assembly shiftr 3 (signed
number)
 Intel shr 3 (unsigned
number)
sar 3 (signed
number)
 C x >> 3
 left shift position multiplied by
 SIC/XE assembly shiftl 3
 Intel shl 3 (unsigned
number)
sal 3 (signed
number)
(shl and sal the same instruction)
Rotation
 rotate left 1 position
. . .

. . .

. . .

 rotate right 2 position


. . .

 rotate left 2 position


. . .
Rotation with Carry
 rotate right 1 position with carry
. . .

CF . . .

𝒙𝟎 CF . . .

 rotate left position with carry ??

 rotate position with carry ??


SICXE : Instruction Set (4)
CLEAR r 2 B4 1011 0100 r0
RMO r1, r2 2 AC 1010 1100 r2  (r1)
SHIFTL r1, n 2 A4 1010 0100 shift left r1 n bits
SHIFTR r1, n 2 A8 1010 1000 shift right r1 n bits

COMP m ¾ 28 0010 1000 (A) ? (m..m+2)


COMPF m ¾ 88 1000 1000 (F) ? (m..m+5)
COMPR r1, r2 2 A0 1010 0000 (r1) ? (r2)

TIX m ¾ 2C 0010 1100 X  (X)+1; (X)?(m..m+2)


TIXR r 2 B8 1011 1000 X  (X)+1; (X)?(r)

FIX 1 C4 1100 0000 A := (F)


FLOAT 1 C0 1100 0000 F := (A)
NORM 1 C8 1100 1000 F := normalized (F)

SSK m ¾ EC 1100 1100 key protection


SVC n 2 B0 1011 0000 supervisor call (SW
interrupts)
SICXE : Instruction Set (5)
HIO 1 F4 1111 0100 halt ch. no. (A)
SIO 1 F0 1111 0000 Start ch. no. (A)
TIO 1 F8 1111 1000 Test ch. no. (A)

TD m ¾ E0 1100 0000 test if channel busy


RD m ¾ D8 1101 1000 A[l.s.b]= read channel
WD m ¾ DC 1101 1100 write channel A[l.s.b]

J m ¾ 3C 0011 1100 PC := m
JEQ m ¾ 30 0011 0000 if (ZF==1) PC := m
JGT m ¾ 34 0011 0100 if (OF==SF && ZF==0) PC :=
m
JLT m ¾ 38 0011 1000 if (OF!=SF && ZF==0) PC :=
m

RSUB ¾ 4C 0100 1100 PC  (L)


JSUB m ¾ 48 0100 1000 L  (PC); PC  m
Format Representation (1)
Format 1 opcode8 1 byte

Format 2 opcode8 r14 24bytes


r2

Format 3 3 bytes
opcode6 n i x b p e disp12

Format 4 4bytes
opcode6 n i x b p e addr20
SICXE CPU
 Architecture

 Memory

 Registers

 Data Formats

 Instructional Formats

 Addressing Modes

 Instruction Set

 Input / Output
SICXE : Input / Output
 transferring 1 byte at a time to/from a device
 TD : test device
 if it is ready for action (read or write)

 repeat testing until the device is available (not


busy)
 WD : write data (a byte) to device
 RD : read data (a byte) from device

newly added controls


 SIO : start I/O channel
 TIO : test I/O channel
 HIO : halt I/O channel
1.3.3 SIC Programming
alpha RESW 1
five word 5
charZ byte C’Z’
c1 RESB 1
...
LDA five load constant 5 into reg. A
STA alpha store in alpha
LDCH charZ load char ‘Z’ into reg A
STCH c1 store in char. variable c1
...

alpha RESW 1
c1 RESB 1
...
LDA #5 load constant 5 into reg. A
STA alpha store in alpha
LDCH #90 load char ‘Z’ into reg A
STCH c1 store in char. variable c1
...
Example 2
one word alpha resw 1
1 beta resw 1
alpha resw gamma resw 1
1
delta resw 1
beta resw
1 incr resw 1
gamma resw . . .
1 LDS incr
delta resw LDA alpha
1
ADDR S,A
incr resw
1 SUB #1
. . . STA beta
LDA alpha LDA
gamma
ADD incr
ADDR S,A
SUB one
SUB #1
S TA beta
STA delta
LDA gamma
ADD incr
Example 3
str1 BYTE C’test str1 BYTE C’test
string’ string’
str2 RESB 11 str2 RESB 11
zero word 0 . . .
eleven word 11 LDT #11
... LDX #0
LDX zero
movch LDCH str1,X
movch LDCH str1,X
STCH str2,X
STCH str2,X
TIX eleven TIXR T
JLT movch JLT movch
... . . .
t e s t s t r i n g

str1
, X 2
0
3
1
4
str2
,
t e s t
Example 4
index resw 1
alpha resw 100 index resw 1
beta resw 100
alpha resw 100
gamma resw 100
zero word 0 beta resw 100
K300 word 300 gamma resw 100
three word 3
LDS #3
LDA zero
LDT #300
STA index
addlp LDX index LDX #0
LDA alpha, X addlp LDA alpha, X
ADD beta, X ADD beta, X
STA gamma, X STA gamma, X
LDA index
ADD three ADDR S, X
STA index COMPR X, T
COMP K300 JLT addlp
JLT addlp
Example 5
indev byte X’F1’
outdev byte X’05’
data RESB 1
. . .
inloop TD indev busy-wait-loop
JEQ inloop
RD indev
STCH data
. . .
outloop TD outdev busy-wait-loop
JEQ outloop
LDCH data
WD outdev
Example 6
JSUB read JSUB read

indev byte x’F1’ indev byte x’F1’


record RESB 100 record RESB 100
zero word 0
k100 word 100
read LDX #0
LDT #100
read LDX zero rloop TD indev
rloop TD indev JEQ rloop
JEQ rloop RD indev
RD indev STCH record, X
STCH record, X TIXR T
TIX k100 JLT rloop
JLT rloop RSUB
RSUB
1.4 Some Real Architectures
 IBM 370/360 main frame
 main-frame : very nice design

 SunMicro System
 workstation
 RISC CPU
 SunOS (Unix-like)

 POWER PC
 IBM / Motorola / Apple joint development
 RISC

 Cray super computer


 first Giga-Hz machine
 vector processor

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