Introduction To FPGA
Introduction To FPGA
pail.phenikaa- thuan.levan@phenikaa-
Content
1.Digital Systems
2.Introduction of HDL
3.FPGAs
4.KIT LP-2900 and Quartus II
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1. Digital Systems
Analog signal Digital signal
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1. Digital Systems (cont.)
Digital systems are designed to store, process, and communicate
information in digital form.
Advantages of digital devices
• Reproducibility of information
• Flexibility and functionality: easier to store, transmit information
• Easier to design and programmable
Moore’s Law
• Chips double its density (number of transistor) in every 18 months
• Devices become smaller, faster, and cheaper
• Now a chip consists of hundreds of million gates
• And we can have a “wireless-PDA-MP3-video-player-camera-GPS-cell-
phone”.
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1. Digital Systems (cont.)
Applications
• “Digitization” has spread to a wide range of applications, including
information (computers), telecommunication, control systems, …
• Digital circuitry replaces many analog systems:
Audio recording: from tape to music CD to MP3 (MPEG Layer 3) player
Image processing: from silver-hand film to digital camera
Telephone switching networks
Control systems
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1. Digital Systems (cont.)
e.g, temperature control system
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2. Introduction of HDL (Design Entry)
Schematics Hardware Description Language
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2. Introduction of HDL
HDL = Hardware Description Language
• Allows for modeling and simulation (with timing) of digital designs
• Can be synthesized into hardware (netlist) by synthesis tools (FPGA
compilers)
• Two major standards in industry and academia
Verilog HDL (Flexible, loose, more common in industry)
VHDL – Very High-Speed Circuit HDL (Strongly typed, more
common in defense and automotive)
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2. Introduction of HDL (cont.)
• Looks similar to a programing language
• It is not a programing language
Programming language => translated into machine instructions that are executed
by a CPU.
HDL => translated into gateware (logic gates & flip-flops)
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2. Introduction of HDL (cont.)
Simulating/Validating HDL
• The sad truth 10% design, 90% validation
• If you do right, you will spend 9 times more than testing/validating
a design than designing it
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2. Introduction of HDL (cont.)
Why Use an HDL?
• Enables Larger Design
More abstracted than schematics, allows larger designs
Work at transistor/gate level for large designs: complicated
• Portable Design
Behavior or dataflow Verilog can be synthesized to a new library with little
effort
Verilog written in ASCII text. The ultimate in portability. Much more portable
than the binary files of a GUI schematic capture tool.
• Explore larger solution space
Synthesis options can help optimize (power, area, speed)
• Better Validated Designs
Verilog itself is used to create the testbench: flexible method that allows self
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3. Introduction of HDL (cont.)
Verilog Versus VHDL
Popularity Commercial and Industrial Defense and Automotive
Applications Systems
Syntax Based on C language and Based on Ada and Pascal
case sensitive languages, not case
sensitive
Flexibility and flexibility and freedom in clearer rules and provides
Control implementing complex stricter control over the
designs, allowing architecture of the
programmers to have hardware model
higher control over design
Development Faster and easier code More suitable for
Time writing, shorter developing large and
development time complex systems
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3. Verilog and VHDL (cont.)
Trend over time
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3. Verilog and VHDL (cont.)
VHDL: Euro, South America, Australia
Verilog: Asia, North America, East Euro
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5. FPGAs
What are FPGA?
A field-programmable gate array
(FPGA) is an integrated circuit
designed to be configured by a
customer or a designer after
manufacturing – hence the term
"field-programmable".
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5. FPGAs (cont.)
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5. FPGA Boards
FPGAs are available as part of circuit boards which contain
multiple optional other peripherals such as switches, LEDs, 7-
segment displays, ADCs and DAC, VGA, etc
Example
FPGAs
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5. FPGAs (cont.)
Architecture: consists of three major components
• Configurable Logic Blocks, which implement logic functions
• Programmable interconnections
• I/O blocks, which are used to make off-chip connections
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5. FPGAs (cont.)
Standard Cells
• Library of common gates and structures (logic-cells)
• A cell includes 1 LUT (Look-up Table), 1 D-Flipflop, and 1 2-1 MUX
• Arrange the cells on the chip: balance between flexible and speed (delay)
• Connect them using programable routing
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5. FPGAs (cont.)
Configurable Logic Blocks
• Use small memories as truth tables of function (LUT)
• A LUT consists of a block of SRAM that can do many different logic
functions.
• The LUT in holds a custom truth table.
• When an FPGA is configured, the bits of the LUT are loaded with ones or
zeros based on what the desired truth table would be.
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5. FPGAs (cont.)
Programmable Interconnects
• Interconnects establish the connection between configurable logic blocks
and Input/Output blocks to complete a user-defined design unit.
• It consists of multiplexers, pass transistors and tri-state buffers.
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5. FPGAs (cont.)
IO-Cells and Internal RAM
• IO-Cells connect I/O pins of the FPGA (user pins and dedicated pins) with
internal logic blocks
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5. FPGAs (cont.)
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5. FPGAs – Design Entry
The design entry is done in different techniques like:
• Schematic based
• HDL
• Combination of both
If the designer wants to deal with hardware, then the schematic entry
is a good choice.
If the designer thinks the design in an algorithmic way, then the HDL
is the better choice
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5. FPGAs – Design Synthesis
This process translates HDL code into a device netlist format, i.e., a
complete circuit with logical elements.
The design synthesis process will check the code syntax and analyze
the hierarchy of the design architecture.
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5. FPGAs – Design Implementation
Translate
• This process combines all the input netlist to the logic design file. Here the
ports are assigned to the physical elements like pins, switches in the design.
Map
• Mapping divides the circuit into sub-blocks such that they can be fit into
the FPGA logic block.
Routing
• The routing process place the sub-blocks from the mapping process into the
logic blocks according to the constraints and then connects the logic
blocks.
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5. FPGAs – Design Programming
The routed design must be loaded into the FPGA
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5. FPGAs – Design Verification
Functional Simulation
• Functional simulation is performed post-translation simulation. It gives the
information about the logical operation of the circuit.
Timing Simulation
• It is done by post mapping. Post mapping report gives the signal path
delays. After place and route, timing report takes the timing delay
information. This provides a complete timing summary of the design.
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5. FPGAs (cont.)
Advantages:
• Parallel computing
• Flexibility and Customizability
• Real-time performance
• Low power consumption
Disadvantages:
• High complexity
• High development time
• Cost
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5. FPGAs - Applications
Applications: due to their flexibility, reconfigurability, and parallel
processing capabilities
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5. FPGAs - Applications
Emulation of entire large hardware systems via the use of many
interconnected FPGAs.
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6. KIT LP-2900 and Quartus II
LP-2900 Logic Lab Platform
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6. KIT LP-2900 and Quartus II (cont.)
Intel Quartus is programmable logic device design software (earlier
Altera Quartus II).
Enables analysis and synthesis of HDL designs, which enables the
developer to compile their designs, perform timing analysis, examine
RTL diagrams, and configure the target device with the programmer.
Includes an implementation of VHDL and Verilog for hardware
description, visual editing of logic circuits, and vector waveform
simulation.
Quartus II 13.1 Student Web Edition is used in this course.
Link:
https://www.intel.com/content/www/us/en/software-kit/666221/intel-
quartus-ii-web-edition-design-software-version-13-1-for-windows.html 36
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