Data Flow Modelling

Style
Levels of Abstraction
 Behavioral or Algorithmic level
• This is the highest level of abstraction provided by Verilog HDL.
• A module can be implemented in terms of the desired design algorithm
without concern for the hardware implementation details.
• Designing at this level is very similar to C programming.

 Dataflow level
• At this level, the module is designed by specifying the data flow.
• The designer is aware of how data flows between hardware registers and
how the data is processed in the design.
 Gate level
• The module is implemented in terms of logic gates and interconnections
between the gates.
• Design at this level is similar to describing a design in terms of a gate-
level logic diagram.

 Switch level
• This is the lowest level of abstraction provided by Verilog.
• A module can be implemented in terms of switches, storage nodes, and
the interconnections between them.
• Design at this level requires knowledge of switch-level implementation
details.
Components of a Verilog Module

Module
Defination:
Verilog code is enclosed with
module and endmodule Keywords.
Here Port list and their
Declarations are Specified
Any Parameter values are also
intialized
Module definations cannot be
nested.
Assignments
• The assignment is the basic mechanism for placing values into nets
and variables.
There are two basic forms of assignments:
1. The continuous assignment, which assigns values to nets/ wires
2. The procedural assignment, which assigns values to variables/reg
Continuous Assignments
• A continuous assignment is the most basic statement in dataflow
modeling, used to drive a value onto a net.
• A continuous assignment statement starts with the keyword assign.
Syntax : assign <list of arguments>;
Example:
input a,b;
output y;
assign y = a&b;
Rules for Continuous Assignment
1. The LHS of an assignment must be a scalar or vector net, it cannot be
a register
2. These are always active. Assignment expression is evaluated as soon
as RHS changes
3. Operands on RHS can be scalar /vector with data type net / register
4. Delays can be given
Examples:
1. assign out = il & i2
2. assign addr[l5:0] = addr1_bits[l5:0]* addr2_bits[l5:0];
// Continuous assign for vector nets. addr is a 16-bit vector net // addrl
and addr2 are 16-bit vector registers.
3. assign {c-out, sum[3:0]) = a[3:0] + b[3:01 + c-in;
// Concatenation. Left-hand side is a concatenation of a scalar net and a
vector net.
Implicit Continuous
Assignment
• A shorthand method of placing a continuous assignment on a net.
• instead of declaring a net and then writing a continuous assignment
on the net, Verilog provides a shortcut by which a continuous
assignment can be placed on a net when it is declared.
EX:
//Regular continuous assignment
wire out;
assign out = in1 & in2;
//Same effect is achieved by an implicit continuous assignment
wire out = in1 & in2;
Delays
• Delay values control the time between the change in a right-hand-
side operand and when the new value is assigned to the left-hand
side.
• Three ways of specifying delays in continuous assignment statements
are regular assignment delay, implicit continuous assignment delay,
and net declaration delay.
Regular Assignment Delay
• If in1 or in2 changes value again before 10 time units when the result
propagates to out
• This property is called inertial delay
Example:
Assign #10 out = a&b;
• When signals in1 and in2 go high at time 20, out goes to a high 10
time units later (time = 30).
Implicit Continuous
Assignment Delay
• An equivalent method is to use an implicit continuous assignment to
specify both a delay and an assignment on the net.
Example:
//implicit continuous assignment delay
wire #l0 out = in1 & in2;
//same as
wire out;
assign #l0 out = in1 & in2;
 Net Declaration Delay
• A delay can be specified on a net when it is declared without putting a
continuous assignment on the net.
• If a delay is specified on a net out, then any value change applied to the
net out is delayed accordingly.
Example:
//Net Delays
wire # 10 out;
assign out = in1 & in2;
//The above statement has the same effect as the following
wire out;
assign #l0 out = in1 & in2;
Example
module and_tb; $monitor($time, "vlaues of a= %0b,b=
%0b,y=%0b",a,b,y);
Reg a,b; a=1;b=1;
wire y; #10; a=0;b=1;

//wire #10 y;//net declaration delay end

//assign y = a&b; endmodule
assign y = a&b; // continous assignmet
//assign #10 y = a&b; // regular
assignment delay
//wire y = a&b; // implicit assignment
// wire #10 y = a&b; // implict
assignment delay

initial begin
a=0;b=0;
• Add wave form
Assignment -4
• Try the above example with different delays and find the difference
• Implement all basic gates with data flow model without any delays &
with delays.
Expressions
• Expressions are constructs that combine operators and operands to
produce a result
Examples
// Examples of expressions. Combines operands and operators
a^b
addr1[20:17] + addr2[20:17]
in1 | in2
Operands
• Operands can be constants, integers, real numbers, nets,
registers, times, bit-select (one bit of vector net or a vector
register), part-select (selected bits of the vector net or register
vector), memories or function calls
Example:
integer count, final-count;
final-count = count + l; //count is an integer operand
real a, b, c;
c = a - b; //a and b are real operands
reg [15:01 regl, reg2;
reg [3 :0] reg-out;
reg-out = regl[3:0] ^ reg2[3:0l; //reg1[3:0] and reg2[3:0] are
//part-select register operands
Operators
1. Concatenation Operator
• The concatenation operator ({}).
• Provides a mechanism to append multiple operands

reg [7:0] a, b, c, d, y;

a = 8'b00000011;
b = 8'b00000100;
c = 8'b00011000;
d = 8'b11100000;

y=
{a[1:0],b[2],c[4:3],d[7:5]};

This is wrong, not all operands are This is the corrected version:
sized:  y[7:0] = {3´b011, 5´b0};
y[7:0] = {3´b011, ´b0};
2. Replication Operator
• Replication is simply the concatenation of a sized expression a fixed
number of times.
• A replication constant specifies how many times to replicate the number
inside the brackets ( {} )

reg [3:0] a;
reg [7:0] y;

a = 4'b1001;
a[7:0] = {4{´b10}}; y=
b[7:0] = {2{5}}; {{4{a[3]}},a};
 3. Conditional Operator
Syntax:
conditional_expression ? true_expression :
false_expression

O = (S == 2'h0) ? A :(S == 2'h1) ? B : (S ==

2'h2) ? C :D;

 The conditional operator is also called the ternary

operator.
 That is because it takes three operands.
2x1 mux using conditional operator
4. Arithmetic Operators
• The arithmetic operators (*, /, %, +, -) produce numerical or unknown
results.

Exampl -3 * 5 => -15

es: -3 / 2 => -1
-3 % 2 => -1
-3 + 2 => -1

 The integer register data type is signed.

 The reg and time register data types are unsigned.
 5. Unary Reduction Operators
• The unary reduction operators (&, |, ^, ^~) produce a 0, 1, or X scalar
value.

& 4'b1110 => | 4'b0000 => 0 ^ 4'b1111

0 | 4'b0001 => 1 => 0
& 4'b1111 => | 4'b000z => x ^ 4'b1110
1 | 4'b000x => x => 1
& 4'b111z => ^ 4'b111z =>
x x
& 4'b111x => ^ 4'b111x =>
x ^~ 4'b1111 x
a & &b a &
=> 1 a | |b
^~ 4'b1110 (&b)
=> 0 a | (|b)
^~ 4'b111z
=> x
^~ 4'b111x
=> x
6.Negation Operators
 The logical negation operator (!) produces a 0, 1, or X scalar
value.
 The bitwise negation operator (~) inverts each individual bit
of the operand.

! 4'b0100 => 0
! 4'b0000 => 1
! 4'b00z0 => x
! 4'b000x => x
~ 4'b01zx => 10xx
7. Shift Operators
 The shift operators (<<, >>) shift the left operand left or
right the number of times given by the right operand.
 The simulator treats the right operand as unsigned (-2 is
+4294967293).
 If the right operand is unknown, the simulator sets the
result unknown.

Exampl
es:
8'b00011000 << 2 =>
01100000
8'b00011000 >> 2 =>
00000110

8'b00011000 >> -2 =>

00000000
 The left shift operator (<<) shifts the left operand left by
the number of positions specified by the right operand.

 The right shift operator (>>) shifts the left operand right by
the number of positions specified by the right operand.
Example

module decoder2x4(q,a);

input a;

output q;

assign q = (4’b0001) << a;

endmodule
8. Relational Operators
 The relational operators (<, <=, >=, >) produce 0, 1, or x
scalar values.
 The relational operators all have the same precedence.
 An unknown operand may produce an unknown result.

Exampl
(4'b1010 < 4'b0110)
es: => 0 (4'b0010 <=
4'b0010) => 1 (4'b1010
< 4'b0x10) => x
(4'b0010 <= 4'b0x10)
=> x (4'b1010 >=
4'b1x10) => x (4'b1x10
> 4'b1x10) => x
(4'b1z10 > 4'b1z10)
=> x
9. Equality Operators
 Equality Operators are classified as:
Logical Equality (==)
Logical In equality (!=)
Case Equality or Identity (===)
Case Inequality (!==)
 10.Logical Equality Operator
 The logical equality (==) and inequality (!=) operators produce
0, 1, or x scalar values.
(4'b0011 == 4'b1010) => 0
(4'b0011 != 4'b1x10) =>
1
(4'b1010 == 4'b1x10) => x
( 4'b1x10 == 4'b1x10) =>
x
 Evaluatesto:( 4'b1z10 == 4'b1z10) =>
x
True (1) if the LHS = RHS values.
False (0) if the LHS = RHS.
Unknown (X) if the LHS and RHS could be equal.
 11. Case Equality (Identity)
Operators
 The case equality (===) and inequality (!==) operators produce
only 0 and 1 scalar values.
Exampl
es: ( 4'b01zx === 4'b01zx
=>1
( 4'b01zx !== 4'b01zx )
=> 0
( 4'b01zx === 4'b00zx )
 The case equality
=> 0 operators are also called the identity
operators because they
( 4'b01zx !== test to ) see if the operands are
4'b11zx
=>1
identical.
An expression with the case equality operator
evaluates to:
True (1) if every bit of the LHS is identical to its
corresponding RHS bit
False (0) if any bit of the LHS is not identical to its
corresponding RHS bit
The case inequality operator (!==) is the inverse of
the case equality (===) operator.
 12. Bit-Wise Operators
 The bit-wise operators (&, |, ^, ^~) operate on each individual bit
of a vector.
Exampl
es:
(4'b01zx & 4'b0000) =>
0000
(4'b01zx & 4'b1100) =>
0100
(4'b01zx & 4'b1111) =>
01xx
(4'b01zx | 4'b1111) =>
1111
(4'b01zx | 4'b0011) =>
0111
(4'b01zx | 4'b0000) =>
 13. Logical Operators
 The logical operators (&&, ||) produce a 0, 1, or X scalar value:
An operand is logically false if all of its bits are 0.
An operand is logically true if any of its bits are 1.
 Logical binary operators operate on logic values.
( 2'b00 && 2'b10 )
 If an operand contains all zeroes, it is false => 0
( 2'b01 && 2'b10 )
(logic 0). => 1
 If it contains any ones, it is true (logic 1). ( 2'b0z && 2'b10 )
=> x
 If it contains unknowns and no ones, its ( 2'b0x && 2'b10 )
logical value is unknown. => x
( 2'b1x && 2'b1z )
=> 1
( 2'b00 || 2'b00 )
=> 0
2x1 Multiplexer in Dataflow
Using Bit-wise Operator
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b);
endmodule

Using Conditional Operator

module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = sel ? b : a;
endmodule
Using parameter
module mux21n(q, sel, a, b);

parameter WID = 16;

input sel;
input [WID-1:0] a, b;
output [WID-1:0] q;

assign q = sel ? b : a;
endmodule
Operator Precedence:
Verilog greater than or
Name Functional Group >= relational
Operator equal to
[] bit-select or part-select < less than relational
() parenthesis
less than or
! logical negation logical <= relational
equal to
~ negation bit-wise
& reduction AND reduction == logical equality equality
| reduction OR reduction logical
~& reduction NAND reduction != equality
inequality
~| reduction NOR reduction
^ reduction XOR reduction === case equality equality
~^ or ^~ reduction XNOR reduction
!== case inequality equality
+ unary (sign) plus arithmetic
- unary (sign) minus arithmetic
& bit-wise AND bit-wise
{} concatenation concatenation
{{ }} replication replication ^ bit-wise XOR bit-wise
* multiply arithmetic
^~ or ~^ bit-wise XNOR bit-wise
/ divide arithmetic
% modulus arithmetic | bit-wise OR bit-wise
+ binary plus arithmetic
- binary minus arithmetic && logical AND logical
<< shift left shift || logical OR logical
>> shift right shift
?: conditional conditional
Assignment -5
• Write Verilog Code in Dataflow for 4x2 encoder
• Write Verilog Code in Dataflow for Full adder
• Write Verilog Code for 8x1 Mux using Conditional Operator
• Implement Nand, Nor,Xor,Xnor gates using Mux and Verify with
Verilog code