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1.VERILOG HDL - Introduction

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8 views18 pages

1.VERILOG HDL - Introduction

Uploaded by

sricharan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Verilog Basic Concepts

CHAPTER - I
INTRODUCTION
• Evolution of HDL
• Importance of HDL
• Trends in HDL
• Significance of Verilog HDL
• Typical Design Flow
• Design Methodologies
• Modules & Instances
• Simulation components
I. Evolution of HDL
• SSI (Small Scale Integration)

• MSI (Medium Scale Integration)

• LSI (Large Scare Integration)

• VLSI (Very Large Scale Integration)


II. Importance of
HDL
• Designers can write their RTL description without choosing a
specific fabrication technology. Logic synthesis tools can
automatically convert the design to any fabrication technology
• If a new technology emerges, designers do not need to redesign
their circuit
• Since designers work at the RTL level, they can optimize and
modify the RTL description until it meets the desired
functionality
• A textual description with comments is an easier way to develop
and debug circuits.
III. Trends in HDL
• HDL at an RTL
• Verilog Keeps on updates
• Verilog-95,2001,2005,2009
• Supports verification methodologies
• Assertion checking techniques
• Support for automatic stimulus creation(test bench)
IV.Significance of Verilog
HDL
• Verilog HDL has evolved as a standard hardware description
language.
• Verilog HDL is a general-purpose hardware description language
that is easy to learn and easy to use
• Verilog HDL allows different levels of abstraction to be mixed in
the same model.
• The Programming Language Interface (PLI) is a powerful feature
that allows the user to write custom C code to interact with the
internal data structures of Verilog.
V. Typical Design
Flow
• A typical design flow for designing VLSI IC circuits is shown in
Fig. Un shaded blocks show the level of design representation;
shaded blocks show processes in the design flow.
• In any design, specifications are written first. Specifications
describe abstractly the functionality, interface, and overall
architecture of the digital circuit to be designed.
• At this point, the architects do not need to think about how
they will implement this circuit.
• A behavioral description is then created to analyze the design in terms of
functionality, performance, compliance to standards, and other high-
level issues. Behavioral descriptions can be written with HDLs.
• The behavioral description is manually converted to an RTL description
in an HDL.
• Logic synthesis tools convert the RTL description to a gate-level netlist
• The gate-level netlist is input to an Automatic Place and Route tool,
which creates a layout. The layout is verified and then fabricated on
chip.
VI. Design
Methodologies
Two basic types of digital design methodologies:
1. Top-Down Design Methodology
• we define the top-level block
• Identify the sub-blocks necessary to build the top-level block
• Further subdivide the sub-blocks until we come to leaf cells, which are
the cells that cannot further be divided
2. Bottom-Up Design Methodology
• Identify the building blocks that are available to us
• Build bigger cells using these building blocks
• Bigger cells used for higher-level blocks until we build the top-level block
in the design
Example: 4-bit Ripple Carry counter
Modules
• A Module is a basic building block
Syntax : module <module_name>
(<module_terminal_list>);
<module internals>
endmodule
Example : module T-FF (q, clock, reset);
functionality of T-Flipflop
endmodule
<module internals>
a. data flow e. Gate level
b. behavioral f. Switch level
c. structural
d. Mixed modeling
Instances
• A module provides a template from which you can create
actual objects.
• The process of creating objects from a module template is
called instantiation, and the objects are called instances.
• An instance of a module has a unique identity and is
different from other instances of the same module. Each
instance has an independent copy of the internals of the
module.
Example: Ripple carry counter
module ripple-carry-counter(q, clk, reset);
output [3:0] q;
input clk, reset;
T-FF tffO (q[O],clk, reset);
T-FF tffl (q[l] ,q[0], reset);
T-FF tff2 (q[2] ,q[l] , reset) ;
T-FF tff3(q[3] ,q[2], reset) ;
endmodule
Simulation
Components
• Once a design block is completed, it must be tested. The functionality of the
design block can be tested by applying stimulus and checking results. We
call such a block the stimulus block.
• The stimulus block is also commonly called a test bench.
• Two styles of stimulus application are possible.
• The second style of applying stimulus is to instantiate both the
stimulus and design blocks in a top-level dummy module. The
stimulus block interacts with the design block only through the
interface.
Ex: module stimulus;
reg clk;
reg reset;
wire[3:01 q;
ripple-carry-counter rl(q, clk, reset);
initial clk = l'bO;
always #5 clk = -clk;
initial begin
reset = l'bl;
#l5 reset = l'bO;
#l80 reset = l'bl;
#l0 reset = l'bO;
#20 $finish;
initial $monitor ($time, " Output q = %d" , q) ;
endmodule
Add And gate dut and tb
Add script file
execution steps along
with waveform

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