CSE 431

Computer Architecture
Fall 2005

Lecture 05: Basic MIPS Architecture

Review
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg431

[Adapted from Computer Organization and Design,

Patterson & Hennessy, © 2005, UCB]

CSE431 L05 Basic MIPS Architecture.1 Irwin, PSU, 2005

 Review: THE Performance Equation
 Our basic performance equation is then
CPU time = Instruction_count x CPI x clock_cycle
or
Instruction_count x CPI
CPU time = -----------------------------------------------
clock_rate

 These equations separate the three key factors that

affect performance
 Can measure the CPU execution time by running the program
 The clock rate is usually given in the documentation
 Can measure instruction count by using profilers/simulators
without knowing all of the implementation details
 CPI varies by instruction type and ISA implementation for which
we must know the implementation details
CSE431 L05 Basic MIPS Architecture.2 Irwin, PSU, 2005
 So the first area of craftsmanship is in trading
function for size. … The second area of
craftsmanship is space-time trade-offs. For a
given function, the more space, the faster.
The Mythical Man-Month, Brooks, pg. 101

CSE431 L05 Basic MIPS Architecture.3 Irwin, PSU, 2005

 The Processor: Datapath & Control
 Our implementation of the MIPS is simplified
 memory-reference instructions: lw, sw
 arithmetic-logical instructions: add, sub, and, or, slt
 control flow instructions: beq, j
 Generic implementation Fetch
PC = PC+4
 use the program counter (PC) to supply
the instruction address and fetch the Exec Decode
instruction from memory (and update the PC)
 decode the instruction (and read registers)
 execute the instruction
 All instructions (except j) use the ALU after reading the
registers

How? memory-reference? arithmetic? control flow?

CSE431 L05 Basic MIPS Architecture.4 Irwin, PSU, 2005
 Clocking Methodologies
 The clocking methodology defines when signals can be
read and when they are written
 An edge-triggered methodology
 Typical execution
 read contents of state elements
 send values through combinational logic
 write results to one or more state elements
State Combinational State
element logic element
1 2

clock

one clock cycle

 Assumes state elements are written on every clock
cycle; if not, need explicit write control signal
 write occurs only when both the write control is asserted and the
clock edge occurs
CSE431 L05 Basic MIPS Architecture.5 Irwin, PSU, 2005
 Fetching Instructions
 Fetching instructions involves
 reading the instruction from the Instruction Memory
 updating the PC to hold the address of the next instruction

Add

Instruction
Memory
Read
PC Instruction
Address

 PC is updated every cycle, so it does not need an explicit

write control signal
 Instruction Memory is read every cycle, so it doesn’t need an
explicit read control signal
CSE431 L05 Basic MIPS Architecture.6 Irwin, PSU, 2005
 Decoding Instructions
 Decoding instructions involves
 sending the fetched instruction’s opcode and function field
bits to the control unit

Control
Unit

Read Addr 1
Read
Register
Read Addr 2 Data 1
Instruction
File
Write Addr Read
Data 2
Write Data

 reading two values from the Register File

- Register File addresses are contained in the instruction

CSE431 L05 Basic MIPS Architecture.7 Irwin, PSU, 2005

 Executing R Format Operations
 R format operations (add, sub, slt, and, or)
31 25 20 15 10 5 0
R-type: op rs rt rd shamt funct

 perform the (op and funct) operation on values in rs and rt

 store the result back into the Register File (into location rd)
RegWrite ALU control

Read Addr 1
Read
Register
Instruction Read Addr 2 Data 1 overflow
File zero
Write Addr ALU
Read
Data 2
Write Data

 The Register File is not written every cycle (e.g. sw), so we need
an explicit write control signal for the Register File
CSE431 L05 Basic MIPS Architecture.8 Irwin, PSU, 2005
 Executing Load and Store Operations
 Load and store operations involves
 compute memory address by adding the base register (read from
the Register File during decode) to the 16-bit signed-extended
offset field in the instruction
 store value (read from the Register File during decode) written to
the Data Memory
 load value, read from the Data Memory, written to the Register
File RegWrite ALU control MemWrite

overflow
Read Addr 1 zero
Read Address
Register
Instruction Read Addr 2 Data 1 Data
File Memory Read Data
Write Addr ALU
Read
Data 2 Write Data
Write Data

Sign MemRead
16 Extend 32

CSE431 L05 Basic MIPS Architecture.9 Irwin, PSU, 2005

 Executing Branch Operations
 Branch operations involves
 compare the operands read from the Register File during decode
for equality (zero ALU output)
 compute the branch target address by adding the updated PC to
the 16-bit signed-extended offset
field in the instr
Add Branch
4 Add target
Shift address
left 2

ALU control
PC

Read Addr 1 zero (to branch

Register
Read control logic)
Read Addr 2 Data 1
Instruction
File
Write Addr ALU
Read
Data 2
Write Data

Sign
16 Extend 32
CSE431 L05 Basic MIPS Architecture.10 Irwin, PSU, 2005
 Executing Jump Operations
 Jump operation involves
 replace the lower 28 bits of the PC with the lower 26 bits of the
fetched instruction shifted left by 2 bits

Add

4
4
Jump
Instruction
Shift address
Memory
left 2 28
Read
PC Instruction
Address 26

CSE431 L05 Basic MIPS Architecture.11 Irwin, PSU, 2005

 Creating a Single Datapath from the Parts
 Assemble the datapath segments and add control lines
and multiplexors as needed
 Single cycle design – fetch, decode and execute each
instructions in one clock cycle
 no datapath resource can be used more than once per
instruction, so some must be duplicated (e.g., separate
Instruction Memory and Data Memory, several adders)
 multiplexors needed at the input of shared elements with
control lines to do the selection
 write signals to control writing to the Register File and Data
Memory

 Cycle time is determined by length of the longest path

CSE431 L05 Basic MIPS Architecture.12 Irwin, PSU, 2005

 Fetch, R, and Memory Access Portions

Add
RegWrite ALUSrc ALU control MemWrite MemtoReg
4
ovf
zero
Instruction Read Addr 1
Read Address
Memory Register
Read Addr 2 Data 1 Data
Read File
PC Instruction Memory Read Data
Address Write Addr ALU
Read
Data 2 Write Data
Write Data

MemRead
Sign
16 Extend 32

CSE431 L05 Basic MIPS Architecture.13 Irwin, PSU, 2005

 Adding the Control
 Selecting the operations to perform (ALU, Register File
and Memory read/write)
 Controlling the flow of data (multiplexor inputs)
31 25 20 15 10 5 0
R-type: op rs rt rd shamt funct
 Observations 31 25 20 15 0

I-Type: op rs rt address offset
op field always
in bits 31-26 31 25 0
 addr of registers J-type: op target address
to be read are
always specified by the
rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is
the base register
 addr. of register to be written is in one of two places – in rt (bits 20-16)
for lw; in rd (bits 15-11) for R-type instructions
 offset for beq, lw, and sw always in bits 15-0
CSE431 L05 Basic MIPS Architecture.14 Irwin, PSU, 2005
 Single Cycle Datapath with Control Unit
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Read Address
Memory Register
Instr[20-16] Read Addr 2 Data 1 zero
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control

Instr[5-0]

CSE431 L05 Basic MIPS Architecture.15 Irwin, PSU, 2005

 R-type Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr
Instruction
1 Read Address
Memory Register
Instr[20-16] Read Addr 2 Data 1 zero
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control

Instr[5-0]

CSE431 L05 Basic MIPS Architecture.16 Irwin, PSU, 2005

 Load Word Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Read Address
Memory Register
Instr[20-16] Read Addr 2 Data 1 zero
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control

Instr[5-0]

CSE431 L05 Basic MIPS Architecture.18 Irwin, PSU, 2005

 Branch Instruction Data/Control Flow
0
Add
Add 1
4 Shift
left 2 PCSrc
ALUOp Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Read Address
Memory Register
Instr[20-16] Read Addr 2 Data 1 zero
Data
Read
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign ALU

16 Extend 32 control

Instr[5-0]

CSE431 L05 Basic MIPS Architecture.20 Irwin, PSU, 2005

 Adding the Jump Operation
Instr[25-0] 1
Shift 28 32
26 left 2 0
PC+4[31-28]
Add 0
Add 1
4 Shift
Jump left 2 PCSrc
ALUOp
Branch
MemRead
Instr[31-26] Control MemtoReg
Unit MemWrite
ALUSrc

RegWrite
RegDst
ovf
Instr[25-21] Read Addr 1
Instruction
Read Address
Memory Register
Instr[20-16] Read Addr 2 Data 1 zero
Read Data
PC Instr[31-0] 0 File
ALU Memory Read Data 1
Address Write Addr
1 Read 0
Instr[15 Data 2 Write Data 0
Write Data
-11] 1

Instr[15-0] Sign
ALU
16 Extend 32 control

Instr[5-0]

CSE431 L05 Basic MIPS Architecture.21 Irwin, PSU, 2005

 Single Cycle Disadvantages & Advantages
 Uses the clock cycle inefficiently – the clock cycle must
be timed to accommodate the slowest instruction
 especially problematic for more complex instructions like
floating point multiply

Cycle 1 Cycle 2
Clk

lw sw Waste

 May be wasteful of area since some functional units

(e.g., adders) must be duplicated since they can not be
shared during a clock cycle
but
 Is simple and easy to understand

CSE431 L05 Basic MIPS Architecture.22 Irwin, PSU, 2005

 Multicycle Datapath Approach
 Let an instruction take more than 1 clock cycle to
complete
 Break up instructions into steps where each step takes a cycle
while trying to
- balance the amount of work to be done in each step
- restrict each cycle to use only one major functional unit
 Not every instruction takes the same number of clock cycles

 In addition to faster clock rates, multicycle allows

functional units that can be used more than once per
instruction as long as they are used on different clock
cycles, as a result
 only need one memory – but only one memory access per cycle
 need only one ALU/adder – but only one ALU operation per
cycle
CSE431 L05 Basic MIPS Architecture.23 Irwin, PSU, 2005
 Multicycle Datapath Approach, con’t
 At the end of a cycle
 Store values needed in a later cycle by the current instruction in an
internal register (not visible to the programmer). All (except IR) hold data
only between a pair of adjacent clock cycles (no write control signal
needed)

IR
Memory Read Addr 1
PC

A
Address Register Read

ALUout
Read Data Read Addr 2Data 1
File
(Instr. or Data) Write Addr ALU
Read

B
Write Data Write Data Data 2
MDR

IR – Instruction Register MDR – Memory Data Register

 A, B – regfile read data registers ALUout – ALU output register
Data used by subsequent instructions are stored in programmer visible
registers (i.e., register file, PC, or memory)
CSE431 L05 Basic MIPS Architecture.24 Irwin, PSU, 2005
 The Multicycle Datapath with Control Signals
PCWriteCond
PCWrite PCSource
IorD ALUOp
MemRead Control ALUSrcB
MemWrite ALUSrcA
MemtoReg RegWrite
IRWrite RegDst

Instr[31-26]
PC[31-28]

Instr[25-0] Shift 28
left 2 2
0
1
Memory 0
PC

0 Read Addr 1
Address

A
Read
IR

1 Register 1 zero
Read Addr 2 Data 1

ALUout
Read Data
0 File
(Instr. or Data) ALU
Write Addr
1 Read
Write Data Data 2

B
1 Write Data 0
4
MDR

1
0 2
Instr[15-0] Sign Shift 3
Extend 32 left 2 ALU
Instr[5-0] control

CSE431 L05 Basic MIPS Architecture.25 Irwin, PSU, 2005

 Multicycle Control Unit
 Multicycle datapath control signals are not determined
solely by the bits in the instruction
 e.g., op code bits tell what operation the ALU should be doing,
but not what instruction cycle is to be done next
 Must use a finite state machine (FSM) for control
 a set of states (current state stored in State Register)
 next state function (determined Datapath
by current state and the input) Combinational control

...
 output function (determined by control logic points
current state and the input)
...
...
State Reg
Inst Next State
Opcode

CSE431 L05 Basic MIPS Architecture.26 Irwin, PSU, 2005

 The Five Steps of the Load Instruction
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

lw IFetch Dec Exec Mem WB

 IFetch: Instruction Fetch and Update PC

 Dec: Instruction Decode, Register Read, Sign
Extend Offset
 Exec: Execute R-type; Calculate Memory Address;
Branch Comparison; Branch and Jump Completion
 Mem: Memory Read; Memory Write Completion; R-
type Completion (RegFile write)
 WB: Memory Read Completion (RegFile write)
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
CSE431 L05 Basic MIPS Architecture.27 Irwin, PSU, 2005
 Multicycle Advantages & Disadvantages
 Uses the clock cycle efficiently – the clock cycle is
timed to accommodate the slowest instruction step
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10
Clk

lw sw R-type
IFetch Dec Exec Mem WB IFetch Dec Exec Mem IFetch

 Multicycle implementations allow functional units to be

used more than once per instruction as long as they
are used on different clock cycles
but
 Requires additional internal state registers, more
muxes, and more complicated (FSM) control
CSE431 L05 Basic MIPS Architecture.28 Irwin, PSU, 2005
 Single Cycle vs. Multiple Cycle Timing
Single Cycle Implementation:

Cycle 1 Cycle 2
Clk

lw sw Waste
multicycle clock
slower than 1/5th of
Multiple Cycle Implementation: single cycle clock
due to state register
overhead
Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10

lw sw R-type
IFetch Dec Exec Mem WB IFetch Dec Exec Mem IFetch

CSE431 L05 Basic MIPS Architecture.29 Irwin, PSU, 2005

 Next Lecture and Reminders
 Next lecture
 MIPS pipelined datapath review
- Reading assignment – PH, Chapter 6.1-6.3

 Reminders
 HW2 due September 27th
 Evening midterm exam scheduled
- Tuesday, October 18th , 20:15 to 22:15, Location 113 IST
- You should have let me know by now if you have a conflict !!

CSE431 L05 Basic MIPS Architecture.30 Irwin, PSU, 2005