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VHDL

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Abdelali El Bdouri
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9 views19 pages

VHDL

Uploaded by

Abdelali El Bdouri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Introduction to VHDL

(CS 570)

Jeremy R. Johnson
Wed. Nov. 8, 2000

Apr. 3, 2000 Systems Architecture I 1


Introduction
• Objective: To provide an introduction of digital design and
simulation. To introduce the hardware description language
VHDL and the VHDL simulator and design tool Active-HDL.

• Behavioral models
• Structural models
• Discrete event simulation
– signals
– events
– waveforms
– concurrency

Apr. 3, 2000 Systems Architecture I 2


VHDL

• VHSIC Hardware Description Language


– Very High Speed Integrated Circuit
• IEEE standard
– IEEE 1076-1987
– IEEE 1076-1993

• A language for describing digital designs with several


levels of abstraction
– behavioral (describe what the design does)
– structural (describe how the design is implemented)

• Tools exist for verifying designs and synthesizing hardware


layout from designs specified in VHDL
Apr. 3, 2000 Systems Architecture I 3
VHDL Simulation

• Since a VHDL program is a description of a design it, by


itself, does not compute anything

• To verify a design, it must be simulated on a set of inputs

• Computation is “event driven”


– when inputs change (an event) the corresponding outputs are
computed using rules specified in the design
– The state of the design may also change (sequential logic - e.g.
memory, registers, or any state variables)
– changes propagate throughout the system
– there may be delays
– operations may occur concurrently

Apr. 3, 2000 Systems Architecture I 4


VHDL constucts

• Entity
• Port
• Architecture
– implementation of an entity
– support for both behavioral and structural models
• Signal
– std_ulogic (from IEEE 1164 library)
– input/output signals
– internal signals inside an architecture
– assignment
– delays
• Vectors of signals (bus)

Apr. 3, 2000 Systems Architecture I 5


Half Adder

entity half_adder is
port(a,b : in std_ulogic;
sum,carry : out std_ulogic);
end half_adder;

a
sum
b

carry

Apr. 3, 2000 Systems Architecture I 6


MUX

entity mux is
port(I0, I1, I2, I3 : in std_ulogic;
Sel : in std_ulogic_vector (1 downto 0);
Z : out std_ulogic);
end mux;

I0
I1
Z
I2
I3

Sel

Apr. 3, 2000 Systems Architecture I 7


32-Bit ALU

entity ALU32 is
port(a,b : in std_ulogic_vector (31 downto 0);
Op : in std_ulogic_vector (2 downto 0);
result : in std_ulogic_vector (31 downto 0);
zero : out std_ulogic;
Op
CarryOut : out std_ulogic;
overflow : out std_ulogic); a
Zero
end ALU32;
Result
Overflow
b

CarryOut

Apr. 3, 2000 Systems Architecture I 8


Half Adder Behavioral Implementation
library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port(a,b : in std_ulogic;
sum,carry : out std_ulogic);
end half_adder;

architecture concurrent_behavior of half_adder is


begin
sum <= (a xor b) after 5 ns;
carry <= (a and b) after 5 ns;
end concurrent_behavior;
Apr. 3, 2000 Systems Architecture I 9
Half Adder Structural Implementation
library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port(a,b : in std_ulogic;
sum,carry : out std_ulogic);
end half_adder;

architecture structural of half_adder is


component and_2
port(x,y : in std_logic;
c : out std_logic);
end component
Apr. 3, 2000 Systems Architecture I 10
Half Adder Implementation (cont)
component xor_2
port(x,y : in std_logic;
c : out std_logic);
end component;

begin
X1 : xor_2 port map(x => a, y => b, c =>sum);
A1 : and_2 port map(x => a, y => b, c => carry);
end structural;

Apr. 3, 2000 Systems Architecture I 11


Simulation Model

• Signal changes are called events

• Whenever an input signal changes the output is


recomputed
– changes are propogated
– there may be a delay

• Updates occur concurrently

• The history of changes on a signal produces a waveform


(value vs. time)
– shows delays and dependencies

Apr. 3, 2000 Systems Architecture I 12


Boolean Functions
• A boolean variable has two
possible values (true/false) s x0 x1 f
(1/0). 0 0 0 0
• A boolean function has a 0 0 1 0
x0
number of boolean input 0 1 0 1
variables and has a f 0 1 1 1
boolean valued output. x1 1 0 0 0
• A boolean function can be 1 0 1 1
described using a truth 1 1 0 0
table s 1 1 1 1

• There are 22n boolean


function of n variables. Multiplexor function

Apr. 3, 2000 Systems Architecture I 13


Boolean Expressions

• A boolean expression is a boolean function.

• Any boolean function can be written as a boolean expression


s x0 x1 f
– Disjunctive normal form (sums of products)
0 0 0 0
– For each row in the truth table where the output is
true, write a product such that the corresponding 0 0 1 0
input is the only input combination that is true 0 1 0 1
– Not unique 0 1 1 1
1 0 0 0
• E.G. (multiplexor function)
1 0 1 1

s  x0  x1 + s  x0  x1 + s  x0  x1 + s  x0  x1 1 1 0 0
1 1 1 1

Apr. 3, 2000 Systems Architecture I 14


Simplification of Boolean Expressions

• Simplifying multiplexor expression using Boolean algebra

s  x0  x1 + s  x0  x1 + s  x0  x1 + s  x0  x1

= s  x0  x1 + s  x0  x1 + s  x1  x0 + s  x1  x0 (commutative law)

= s  x0  (x1 + x1) + s  x1  (x0 + x0) (distributive law)

= s  x0  1 + s  x1  1 (inverse law)

= s  x0 + s  x1 (identity law)
• Verify that the boolean function corresponding to this expression
as the same truth table as the original function.

Apr. 3, 2000 Systems Architecture I 15


Logic Circuits
• A single line labeled x is a logic circuit. One end is the input
and the other is the output. If A and B are logic circuits so
are:

A
• and gate B

A
• or gate B

• inverter (not) A

Apr. 3, 2000 Systems Architecture I 16


Logic Circuits
• Given a boolean expression it is easy to write down the
corresponding logic circuit
• Here is the circuit for the original multiplexor expression

x0

x1

Apr. 3, 2000 Systems Architecture I 17


Logic Circuits
• Here is the circuit for the simplified multiplexor expression

x0

x1

Apr. 3, 2000 Systems Architecture I 18


Multiplexer
• A multiplexor is a switch which routes n inputs to one output.
The input is selected using a decoder.
d0

d1

d2

d3

s1 s0
Apr. 3, 2000 Systems Architecture I 19

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