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Chapter 4 CMOS

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Alemayehu Guta
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35 views17 pages

Chapter 4 CMOS

Uploaded by

Alemayehu Guta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Chapter Four

CMOS
Outline

• What is CMOS?
• CMOS circuit basics
• Push-pull logic
• Logic gates in CMOS
• Invertor
• NAND
• NOR
What is CMOS?

• A circuit composed of the P-channel and N-


channel MOSFET

• Consists of two transistor networks nMOS


and pMOS

• A technology used for constructing IC

• Has a low power consumption


CMOS circuit basics

• When MOS transistors are used as


logic gate then they are used as a
switch.

• In both NMOS and PMOS transistor,


the voltage applied between the
gate and source acts as switch
control voltage.
CONT…

• NMOS is closed with HIGH logic and


opened with LOW logic

• PMOS is closed with LOW logic and


opened with HIGH logic
Push-pull logic

• CMOS logic uses both NMOS and


PMOS transistors.

• The PMOS transistors are used as


pull-up network and NMOS
transistors are used as pull-down
network
CONT…
• The transistor network is related to the Boolean function with a

straight forward design procedure

• Pull up network design: PMOS • Pull down network design: NMOS

• Connect AND (product) terms in • Connect AND (product) terms in

parallel series

• Connect OR (sum) terms in series • Connect OR (sum) terms in parallel


CONT…

• Add an inverter to the output to complement the function

• Some functions are , such as NAND, NOR gates do not need an


inverter at the output terminal

• Functions has one or more inputs (MOS transistor)


CMOS INVERTER

• The simplest logic circuit


that uses one nMOS and one
pMOS transistor.

• The nMOS is used in PDN


and the pMOS is used in the
PUN
WORKING OPERATION

• When the input is logic HIGH, then the nMOS transistor is ON and the
pMOS transistor is OFF. Thus, the output is pulled down to ground
(logic 0) since it is connected to ground but not to source VDD

• When the input is logic LOW, then nMOS transistor is OFF and the
pMOS transistor is ON, Thus the output is pulled up to VDD (logic 1)
since it is connected to source via pMOS
CMOS NAND gate

• The two input AND function is expressed by Y = A.B

• To design CMOS NAND gate:

• Step 1: Take complement of Y


• Step 2: Design the PDN: two nMOS in series
• Step 3: Design the PUN: two pMOS in parallel
CMOS NAND GATE
CMOS NOR gate

• The two input OR function is expressed by Y = A+B

• To design CMOS NOR gate:

• Step 1: Take complement of Y


• Step 2: Design the PDN: two nMOS in parallel
• Step 3: Design the PUN: two pMOS in series
CMOS
Assignment

1. Design CMOS AND Gate


2. Design CMOS XOR Gate
3. Design 3-input CMOS OR Gate

Design rule:
• Identify boolean expression
• Draw truth table
• Draw pull-up and pull-down network
• Draw the final CMOS AND gate
• Justify any assumption you have used
Thank you

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