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Introduction To VHDL

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24 views23 pages

Introduction To VHDL

Uploaded by

princehasan78789898
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction to VHDL

Objective

 Quick introduction to VHDL


 basic language concepts
 basic design methodology
 examples
VHDL

VHSIC Hardware
Description Language
--------------------------------------

VHSIC --
Very High Speed Integrated Circuits
Modeling Digital Systems

 VHDL is for coding models of a digital system...


 Reasons for modeling
 requirements specification
 documentation
 testing using simulation
 formal verification
 synthesis
 class assignments
 Goal
 most ‘reliable’ design process, with minimum cost
and time
 avoid design errors!
Basic VHDL Concepts

 Interfaces -- i.e. ports


 Behavior
 Structure
 Test Benches
 Analysis, simulation
 Synthesis
VHDL --

 VHDL is a programming language that allows


one to model and develop complex digital
systems in a dynamic environment.

 Object Oriented methodology like C , C++ can


be observed -- modules can be used and
reused.

 Allows you to designate in/out ports (bits) and


specify behavior or response of the system.
VHDL Intro.--

 Think about Hardware


 Forget everything you know...

 Well, not EVERYTHING ...

 But VHDL is NOT C ...


There are some similarities, as with any
programming language, but syntax and logic
are quite different; so get over it !!
-obviously, this will be a painful transition for
you
3 ways to DO IT -- the VHDL way

• Dataflow
• Behavioral
• Structural

BORING sounding??
well, it gets more exciting with the details !!
:)
Modeling the Dataflow way

• uses statements that defines the actual flow of


data.....
such as,
x <= y -- this is NOT less than equl to
-- remember its not C

this assigns the boolean signal x to the value of


boolean signal y... i.e. x = y
this will occur whenever y changes....
Jumping right in to a Model -- e.g. 1
 lets look at Full Adder model -- ignore the extra junk for now --

 library ieee; use ieee.std_logic_1164.all;

 entity fulladd is
 port(A1,A2,Cin: IN std_logic;
 Sum, Cout: OUT std_logic);
 end fulladd;

 Architecture a of fulladd is
 Begin
 process(A1,A2,Cin)
 Begin
 Sum <= Cin XOR A1 XOR A2;
 Cout <= (A1 AND A2) OR (Cin AND (A1 XOR A2));
 end process;
 end a;
Modeling Interfaces
 Entity declaration
 describes the input/output ports of a module

entity name port names port mode (direction)

entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit ); punctuation
end entity reg4;

reserved words port type


Modeling the Behavior
way
 Architecture body
 describes an implementation of an entity
 may be several per entity
 Behavioral architecture
 describes the algorithm performed by the module
 contains
 process statements, each containing
 sequential statements, including
 signal assignment statements and
 wait statements
VHDL -- goofy syntax to
know..
 Omit entity at end of entity declaration

 Omit architecture at end of architecture body


 Omit is in process statement header

entity reg4 is architecture behav of reg4 is


begin
port ( d0, d1, d2 : in bit process (d0, ... )
d3, en, clk : in bit; ...
q0, q1, q2, q3 : out bit begin
...
); end process ;
end reg4; end behav;
Modeling the Structurural
way
 Structural architecture
 implements the module as a composition of
subsystems
 contains
 signal declarations, for internal interconnections
 the entity ports are also treated as signals
 component instances
 instances of previously declared entity/architecture
pairs
 port maps in component instances
 connect signals to component ports
Structural way...
 Declare corresponding components in architecture body

 Important: include library statements before every entity


 Write Entity of the system
 In architecture declare the signals and write components
before keyword “begin”
 After ‘begin” do port mapping
 End architecture
 Write entity for all components
 Write architecture for all components
Mixed Behavior and
Structure
 An architecture can contain both behavioral and
structural parts
 process statements and component instances
 collectively called concurrent statements
 processes can read and assign to signals
 Example: register-transfer-level (RTL) Model
 data path described structurally
 control section described behaviorally
Test Bench your Model

 Testing a design by simulation


 Use a test bench model
 a Model that uses your Model
 apply test sequences to your inputs
 monitors values on output signals
 either using simulator
 or with a process that verifies correct operation
 or logic analyzer
Analysis

 Check for syntax and logic errors


 syntax: grammar of the language
 logic: how your Model responds to stimuli
 Analyze each design unit separately
 entity declaration
 architecture body
 …
 put each design unit in a separate file -- helps a
lot.
 Analyzed design units are placed in a library
 make sure your Model is truly OOP
Simulation

 Discrete event simulation


 time advances in discrete steps
 when signal values change—events occur
 A processes is sensitive to events on input
signals
 specified in wait statements
 resumes and schedules new values on output
signals
 schedules transactions
 event on a signal if value changes
Simulation Algorithm

 Initialization phase
 each signal is given its initial value
 simulation time set to 0
 for each process
 activate
 execute until a wait statement, then suspend
 execution usually involves scheduling transactions on
signals for later times
Simulation Algorithm

 Simulation cycle
 advance simulation time to time of next
transaction
 for each transaction at this time
 update signal value
 event if new value is different from old value
 for each process sensitive to any of these events,
or whose “wait for …” time-out has expired
 resume
 execute until a wait statement, then suspend
 Simulation finishes when there are no further
scheduled transactions
Basic Design
Methodology
Requirements

RTL Model Simulate

Synthesize

Gate-level
Model Simulate Test Bench

ASIC or FPGA Place & Route

Timing
Model Simulate
VHDL -- conclusion...

 Always think about the hardware


-- you are designing a hardware not solving a
programming problem
 Try to make things simple

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