VHDL

Program
Structure
Entity, Ports and Architecture

Dr. Kuldeep Singh, Dept. of ECE, GJUST Hisar

 Outlines
• VHDL?
• Hardware Abstraction?
• Basic Terminology
• VHDL Program Syntax
• Entity, Ports and Architecture
• Hierarchical design (Design Methodologies)
• Design Example (4-bit Ripple Carry Counter)
• Components of Simulation

2 11/12/2024
 VHDL?
VHDL? VHSIC? VHDL Language can be regarded as
an integrated amalgamation of the
V VHSIC V Very following:
H Hardware H High Sequential language +
Concurrent Language +
D Description S Speed net-list language +
timing specifications +
L Language I Integrated Waveform generation
C Circuit =>VHDL

It is a hardware description language that can be The language not only defines the
used to model a digital system at many levels of syntax but also defines very clear
abstractions, ranging from Algorithms to Gate simulation semantics for each
Level language construct.

Complexity of the digital system being modeled could It is a strongly typed language
vary from a simple logic gate to a complete
electronic system or anything between
 Hardware Abstraction?
• VHDL is used to describe a model for a digital hardware device
• This model specify the external view of the device and one or
more internal view
• The external view specifies the interface of the device through
which it communicates with the other models in its environment
• The internal view of the device specifies the functionality or
structure or device model
Entity Device
1 Model 1
Device Device Model Entity Device
External 2 Model 2
View Device

Digita
l Model Actual Entity Device
Syste Hardware N Model N
m Internal
views VHDL View
 Basic Terminology?
• A hardware abstraction of • Basic Design Units of VHDL
digital system is called an – Entity Declaration
Entity – Architecture Body
Entity E2
– Configuration Declaration
– Package declaration
• An entity X, when used in – Package body
another entity Y, becomes a binding
M1: MX:
component for that entity
E2_A1 E2_A
Entity 2
Entity
Declaratio Entity E3
Hardware Entity E1
n
abstraction of Model
a Digital BX CX
BX
System :
CX
:
: :

Architecture E3_A1 E3_A2 E3_A3

E1_A1 E1_A2 E1_A3
Bodies
Entity and its model A configuration of Entity
 Entity Declaration?
• Name of Entity • The Entity is the VHDL basic building block
• List the Name of interface ports
• All the VHDL designs are implemented by entity.
• Mode of ports
•
You can imagine the entity as a black box with
Types of ports
input and output ports.
Entity entity-name is
[generic (list-of-generic-and-their-
types);]
[port ( list-of-ports-and-their-types);]
End [entity] entity-name;
Port modes

Name of Entity In
Entity HALF_ADDER is Out
Mode of ports Inout
Port ( A : in std_logic; Buffer: can have only one source
B : in std_logic; other connected source should be a buffer
Name of ports
SUM : out std_logic; type
Carry : out std_logic); linkage

Types of ports
End HALF_ADDER;
 Architecture Body?
• The internal details of an entity are specified by an Architecture using the following modelling styles:
– As a set of interconnected components (to represent structure)
Entity HALF_ADDER is
– As a set of concurrent assignment statements (to represent dataflow) Port (A , B : in std_logic;
– As a set of sequential assignment statements (to represent behaviour) SUM, Carry : out
– As any combination of the above three std_logic);
End HALF_ADDER;
Architecture HA_STRUCTURE of Architecture HA_DATAFLOW of
HALF_ADDER is HALF_ADDER is
Component XOR2 Begin
Port (X , Y : in std_logic; Z : out SUM <= A XOR B;
std_logic); Carry <= A AND B;
End component; End HA_DATAFLOW;
Component AND2 Architecture HA_Behavior of
Port (L ,M : in std_logic; N : out HALF_ADDER is
std_logic); Begin
End component; Process (A,B)
Begin SUM <= A XOR B;
X1: XOR2 port map (A,B, SUM); Carry <= A AND B;
A1: AND2 port map (A,B, Carry); End HA_Behavior;
End HA_STRUCTURE;
 Mixing Style Modelling? Architecture FA_MIX of FULL_ADDER is

Component XOR2
Port (P1 , P2 : in std_logic; Pz : out std_logic);
End component;

Signal S1 : Std_logic;

Begin
---
X1: XOR2 port map (A,B, S1); Structural
Process (A,B,Cin)
Variable V1,V2,V3: std_logic; ---Behavior
begin
V1:= A and B;
V2:= B and Cin;
V3:= Cin and A;
Entity FULL_ADDER is Cout<= V1 or V2 or V3;
Port (A , B, Cin : in std_logic; End process;
SUM, Cout : out std_logic);
SUM<= S1 xor Cin; ---Dataflow
End FULL_ADDER;
End FA_MIX;
Hierarchical design (Design Methodologies)
Top-Down design methodology
 Define the top level block and identify the sub-
blocks necessary to build the top-level block.
 Further sub divide the sub-blocks until come to
leaf cells, which are the cells that cannot
further be divided.
Hierarchical design (Design Methodologies)
Bottom-Up design methodology
 Identify the building blocks that are available to us.
 Build bigger cells, using these building blocks.
 These cells are then used for higher-level blocks
until we build the top-level block in the design.
Design Example (4-bit Ripple Carry Adder)

A[3: S[3:
0] 0]
4-Bit
B[3: Full Adder Cout
0]
Cin

B3 A3 B2 A2 B1 A1 B0 A0

Ci
FA3 FA2 FA1 FA0 n
Cou C2 C1 C0
t

S3 S2 S1 S0
 Design Example (4-bit Ripple Carry Adder)
A S
1-Bit
Full Adder Carr
B
y
Cin
 Design Example (4-bit Ripple Carry Adder)

4-Bit Ripple Carry

DESIGN
Full Adder

Full Full Full Full

Adder Adder Adder Adder
(FA3) (FA2) (FA1) (FA0)

AN AN AN AN
XOR OR XOR OR XOR OR XOR OR
D D D D
 Design Example (4-bit Ripple Carry Adder)

4-Bit Ripple Carry

IMPLEMENTATIO
Full Adder
N

Full Full Full Full

Adder Adder Adder Adder
(FA3) (FA2) (FA1) (FA0)

AN AN AN AN
XOR OR XOR OR XOR OR XOR OR
D D D D
 VHDL Design (4-bit Ripple Carry Adder)
library IEEE; Entity FA is
use IEEE.STD_LOGIC_1164.all;
Port (A , B, C: in std_logic;
entity adder_4bit is
port( a, b : in STD_LOGIC_VECTOR(3 downto 0); SUM, Carry : out std_logic);
cin : in STD_LOGIC_VECTOR(3 downto 0); End FA;
cout : out STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0) );
end adder_4bit;

architecture adder_4bit_arc of adder_4bit is Architecture FA_DATAFLOW of FA is

Component fa is
port (a, b, c : in STD_LOGIC; sum, Carry : out STD_LOGIC);
Signal S1, S2,S3,S4: std_logic;
end component;

signal C : std_logic_vector (2 downto 0); Begin

S4 <= A XOR B;
begin SUM <= S4 XOR C;
u0 : fa port map (a(0), b(0), cin, sum(0),C(0)); S1:= A and B;
u1 : fa port map (a(1), b(1), C(0), sum(1), C(1)); S2:= B and C;
u2 : fa port map (a(2), b(2), C(1), sum(2), C(2)); S3:= C and A;
u3 : fa port map (a(3),b(3), C(2), sum(3), Cout);
Carry<= S1 or S2 or S3;
End FA_DATAFLOW;
end adder_4bit_arc;
 Verilog Design of 4-bit Ripple Carry
Counter)
module RippleCarryCounter (q, clk, module Tff (q, clk, reset);
reset);
Output q;
Input clk, reset;
Output [3:0] q;
Input clk, reset;
Wire d;
Dff Dff0 (q, d, clk,reset);
// 4 instances of module Tff are created endmodule
module Dff (q, d,clk, reset);
Output q;

Tff Tff0 (q[0], clk, reset); Input d, clk, reset;

reg q;
Tff Tff1 (q[1], q[0], reset);
always @ (posedge reset or negedge clk)
Tff Tff2 (q[2], q[1], reset); if (reset)
q<=1’b0;
Tff Tff3 (q[3], q[2], reset); else
q<=d;
endmodule endmodule
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 Verilog Design of 4-bit Ripple Carry
module stimulus;
wire [3:0] q;
Counter)
reg clk, reset;
// instances the design_counter
RippleCarryCounter r1 (q, clk, reset);
//control the clock signal
Initial
clk = 1’b0;
Always
#5 clk = ~clk;
Initial
Begin
reset = 1’b1;
#15 reset = 1’b0;
#180 reset = 1’b1;
#10 reset = 1’b0;
#20 $finish;
End
Initial
$monitor($time, “ output q = %d”,
q);
endmodule
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Components of Simulation
• Stimulus Block Instantiates Design Block
• Stimulus and Design Blocks Instantiated
in a dummy Top level module
 Module, ports and instances
Module_na
me
module adder (carry, sum, a, b, cin);
output carry, sum;
input a, b, cin; I/o ports
wire w0, w1, w2,w3; name
I/o ports
declaration
Intermediate connection or wire
xor x0(w3, a, b); declaration
Verilog built-in xor x1(sum, cin,w3);
module / primitive and u1(w0, a, b);
components
and u2(w1, a, cin);
Logic circuit
and u3(w2, cin, b);
description
or u4(carry, w0, w1, w2)
endmodule
Instantiati
on