Module III

Central Processing Unit

Reference
Morris Mano: Computer System Architecture
Made by: ASET Faculties
Modified by: Ishaan Rastogi (BO 2027)

CPU
Performs various data processing operations.
It is a multipurpose, programmable, clock driven register based semiconductor
device.
It interprets instructions given to the computer, performs the arithmetic and logical
processing operations and causes the input and output operations.
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1
 MAJOR COMPONENTS OF CPU

To store intermediate
data used during the Performs the required
execution of the micro operations for
instructions. executing the instructions.

Supervises the transfer of

Transfer components information among the
• Common bus system registers and instructs the
ALU as to which operation
to perform
Fig.1 2
 GENERAL REGISTER
ORGANIZATION

Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output
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Fig.2
 General register based CPU Organization
• Multiple general purpose registers are used instead of single accumulator register.
• Computer uses 2 or 3 address fields in the instruction format where each address field
may specify a general register or a memory word.
• Use of multiple CPU registers for frequently used variables & intermediate results, we
can avoid memory references much of the time, thus increasing program execution speed
and reducing program size.
• The output of each register is connected to 2 MUX to form the 2 buses A & B.
• The A and B buses form the inputs to a common arithmetic logic unit (ALU). The
operation selected in the ALU determines the arithmetic or logic micro operation that is to
be performed.
• The result of the micro operation is available at the output and also goes as input to one of
the registers
• The register that receives the information from the output bus is selected by the decoder.
• The decoder activates one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.
• The control unit that operates the CPU bus system directs the information flow through
the registers & ALU by selecting the various components in the system.

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• For example, to perform the operation R 1 <--R2 + R3
the control unit must provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A
2. MUX B selector (SELB): to place the content of R3 into bus B
3. ALU operation selector (OPR): to provide the arithmetic addition : A + B
4. Decoder destination selector (SELD): to transfer the content of the output bus into R1.
• The 4 control selection variables are generated in the control unit and must be available
at the beginning of a clock cycle.
• The data from the two source registers propagate through the gates in the multiplexers
and the ALU, to the output bus, and into the inputs of the destination register, all during
the clock cycle interval.
Control Word: There are 14 binary selection inputs in the unit & their combined value
specifies a control word. The 14-bit control word is defined as below:

3 3 3 5

SELA SELB SELD OPR

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• The encoding of the register selections is specified in the table
below:
Encoding of Register Selection • When SELA or SELB is 000,
Fields the corresponding multiplexer
selects the external input data.
Binary SELA SELB SELD
Code • When SELD = 000, no
000 INPUT INPUT NONE destination register is selected
001 R1 R1 R1 but the contents of the output
bus are available in the external
010 R2 R2 R2 output.
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
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 Encoding of the ALU operations
• The OPR field has 5 bits and each operation is designated with a symbolic name

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 Stack Organization
• A useful feature included in the CPU of most computers is a stack or last-in, first-
out (LIFO) list.
• It is a storage device that stores information in such a manner that the item stored
last is first item retrieved.
• To keep track of stack locations, there is an address register used to count only
(after an initial value is loaded into it).
• The register that holds the address for the stack is called a stack pointer (SP)
because its value always points at the top item in the stack.
• PUSH & POP: The 2 operations of a stack are the insertion & deletion of items.
• The operation of insertion is called push (or push-down) because it can be thought
of as the result of pushing a new item on top.
• The operation of deletion is called pop (or pop-up) because it can be thought of as
the result of removing one item so that the stack pops up.
• These operations are performed by incrementing or decrementing the stack pointer
register.

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 Register Stack
• A stack can be placed in a portion of a large memory or it can be organized as a collection
of a finite number of register words.
• FULL & EMPTY are 2 flags. SP is Stack Pointer, DR is Data Register.
• SP contains a binary number whose value is equal to
the address of the word that is currently on top of the
stack.
• 3 items are placed in the stack: A, B, and C, such that,
Item C is on top of the stack so that the content of SP is
now 3.
• To remove the top item, the stack is popped by reading
the memory word at address 3 & decrementing the
content of SP.
• Item B will then be on top of the stack & SP will hold
the address 2.
• To insert a new item, the stack is pushed by
incrementing SP & writing a word in the next-higher
64-word Register Stack location in the stack.
• Note that item C has been read out but not physically
removed. This does not matter because when the stack
is pushed, a new item is written in its place. 9
• In a 64-word stack, the SP comprises of 6 bits (2^6 = 64).
• It therefore cannot exceed a number greater than 63 (111111 in binary).
• When 63 is incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary,
but SP can accommodate only the six least significant bits.
• Similarly, when 000000 is decremented by 1, the result is 111111.
• The one-bit register FULL is set to 1 when the stack is full, & the one-bit register
EMTY is set to 1 when the stack is empty.
• DR is the data register that holds the binary data to be written into or read out of the
stack.
• Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so that SP
points to the word at address 0 and the stack is marked empty and not full.
• If the stack is not full (if FULL = 0), a new item is inserted with a push operation.
• A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The
pop operation consists of the following sequence of microoperations:

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Initially, SP = 0, EMTY = 1, FULL = 0
PUSH
SP  SP + 1 Increment SP
M[SP]  DR Write item on top of stack
If (SP = 0) then (FULL  1) Check if stack is full
EMTY  0 Mark the stack not empty

Initially, SP = 0, EMTY = 1, FULL = 0

POP
DR  M[SP] Read item from top of stack
SP  SP – 1 Decrement SP
If (SP = 0) then (EMTY  1) Check if stack is empty
FULL  0 Mark the stack not full

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• A bus-organized CPU similar to Fig. 2 has 16 registers with 32 bits in each, an
ALU, and a destination decoder.
(a) How many multiplexers are there in the A bus, and what is the size of each
multiplexer?
(b) How many selection Inputs are needed for MUX A and MUX B?
(c) How many inputs and outputs are there in the decoder?
(d) How many inputs and outputs are there in the ALU for data, including input and
output carries?
(e) Formulate a control word for the system assuming that the ALU has 35
operations.
• (a) 32 multiplexers, each of size 16 × 1
• (b) 4 inputs each, to select one of 16 registers
• (c) 4-to-16 – line decoder
• (d) 32 + 32 + 1 = 65 data input lines
32 + 1 = 33 data output lines.
• (e) 4 4 4 6 = 18 bits
SELA SELB SELD OPR
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 Memory Stack
• A stack can also be implemented in a random-access memory attached to a CPU.
• The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer.
• The stack pointer SP points at the top of the stack & is used to push or pop items into or
from the stack.
• Either of the 3 registers PC (Program Counter), AR
(Address Register) and SP (Stack Pointer) can provide
an address for memory.
• PC is used during the fetch phase to read an instruction.
• AR is used during the execute phase to read an operand.
• The initial value of SP is 4001 and the stack grows with
decreasing addresses.
• Thus the first item stored in the stack is at address 4000,
the second item is stored at address 3999, and the last
address that can be used for the stack is 3000.
• A portion of memory is used as a stack with a
processor register as a stack pointer.

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Q. A stack is organized such that SP always points at the next empty location on the stack.
This means that SP can be initialized to 4000 as in figure above for memory stack and the
first item in the stack is stored in location 4000. List the micro-operations for the push and
pop operations.
• PUSH: SP  SP - 1
M[SP]  DR

• POP: DR  M[SP]
SP  SP + 1
Q. Let SP = 000000 for the case of 64-word Register stack. How many items are there in
the stack if:
a. FULL = 1 and EMTY = 0? 64
b. FULL = 0 and EMTY = 1? 0

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 Reverse Polish notation (RPN)
• A stack organization is very effective for evaluating arithmetic expressions
• The common mathematical method of writing arithmetic expressions imposes
difficulties when evaluated by a computer
• The common arithmetic expressions are written in infix notation, with each operator
written between the operands.
• A+B Infix notation
• +AB Prefix or Polish notation
• AB+ Postfix or reverse Polish notation
• The reverse Polish notation is in a form suitable for stack manipulation.
• Now consider the stack operations shown in figure below
(3 * 4) + (5 * 6)  34*56*+

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 Problems
Convert the following arithmetic expressions from infix to reverse polish notation.
(i) A * B + C * D + E * F
(ii) A * B + A * (B * D + C * E)
(iii) A + B * [C * D + E * (F + G)]
(iv) A * [B + C * (D + E)] / [F * (G + H)]
ANS
(i) AB * CD * EF * + +
(ii) AB * ABD * CE * + * +
(iii) ABCD*EFG+*+*+
(iv) ABCDE + * + * FGH + */

Convert the following arithmetic expressions from reverse Polish notation to infix
notation
(a) A B C D E + * - /
(b) A B C D E * / * +
(c) A B C */ D - E F / +
(d) A B C D E F G + * + * + *
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 Instruction Formats
• A computer usually has a variety of instruction code formats
• It is the function of the control unit within the CPU to interpret each instruction code &
provide the necessary control functions needed to process the instruction
• Computers may have instructions of different lengths containing varying number of
addresses.
• The number of address fields in the instruction format of a computer depends on the
internal organization of its registers.
• Most computers fall into 1 of 3 types of CPU organizations:
- Single accumulator organization.
- General register organization.
- Stack organization.

1. Single accumulator organization

All operations are performed with an implied accumulator register. The instruction format
in this type of computer uses one address field.
ADD X AC AC + M [X]

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2. General register organization
The instruction format in this type of computer needs 3 register address fields.
• ADD R1 , R2 , R3 R 1 <--- R2 + R 3
• ADD R1 , R2 R 1 <--- R 1 + R2
• MOV R1 , R2 R 1 <-- R2
• ADD R1 , X Rl <--R l + M [X]
3. Stack organization
Computers with stack organization would have PUSH and POP instructions which require an
address field
• PUSH X - The instruction will push the word at address X to the top of the stack. The
stack pointer is updated automatically.
• Operation-type instructions do not need an address field in stack-organized computers.
This is because the operation is performed on the 2 items that are on top of the stack.
• E.g: ADD- This operation has the effect of popping the 2 top numbers from the stack,
adding the numbers, and pushing the sum into the stack.
• There is no need to specify operands with an address field since all operands are implied
to be in the stack.
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 Type of Address Instructions
X = (A + B) * (C + D)
Three-Address Instructions

Two-Address Instructions

One-Address Instructions Zero-Address Instructions

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 Addressing Modes
• The method to define the operands or the location of the operands in the given instruction
• Provides versatility to the programmer by providing such facilities as pointers to memory,
counters for loop control, indexing of data, and program relocation.
• Reduces the number of bits in the addressing field of the instruction.
Implied Addressing Modes
Stack Addressing Modes

Immediate Addressing Modes

Direct Addressing Modes
Indirect Addressing Modes
Register Direct Addressing Modes
Addressing Modes
Register Indirect Addressing Modes
Relative Addressing Modes
Indexed Addressing Modes
Base Register Addressing Modes
Auto-increment Addressing Modes

Auto-Decrement Addressing Modes

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 Types of Addressing Modes
Implied Mode:
• In this mode the operands are specified implicitly in the instruction.
• All register reference instructions that use an accumulator are implied-mode instructions.
E.g. CMA
• Zero-address instructions in a stack-organized computer are implied-mode instructions
since the operands are implied to be on top of the stack.
Stack Mode:
• The operand is contained at the top of the stack. Example: ADD
• This instruction simply pops out 2 symbols contained at the top of the stack.
• The addition of those 2 operands is performed.
• The result so obtained after addition is pushed again at the top of the stack.
Immediate Mode: In this mode the operand is specified in the instruction itself. In other
words, an immediate-mode instruction has an operand field rather than an address field. E.g.
MVI 08H.
Direct Address Mode: AC ← AC + M[X]
• In this mode the effective address is equal to the address part of the instruction.
• The operand resides in memory and its address is given directly by the address field of
the instruction.
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Indirect Address Mode: AC ← AC + M[[X]]
• In this mode the address field of the instruction gives the address where the
effective address is stored in memory
• Control fetches the instruction from memory and uses its address part to access
memory again to read the effective address.

Register Mode:
• In this mode the operands are in registers that reside within the CPU. The particular
register is selected from a register field in the instruction
• A k-bit field can specify any one of 2^k registers. E.g. MOV R1, R2.

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Register Direct Mode
• ADD R will increment the value stored in the accumulator by the content of register
R. AC ← AC + [R]
• ADD R will increment the value stored in the accumulator by the content of
memory location specified in register R. AC ← AC + [[R]]
• This addressing mode is similar to indirect addressing mode. The only difference is
address field of the instruction refers to a CPU register.
Register Indirect Mode:
• In this mode the instruction specifies a register in the CPU whose contents give the address
of the operand in memory.
• The advantage of a register indirect mode instruction is that the address field of the
instruction uses fewer bits to select a register than would have been required to specify a
memory address directly. E.g. LDA 2000H
Auto increment or Auto decrement Mode:
• This is similar to the register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory. (Effective Address of the
Operand = Content of Register +1 )
• When the address is stored in the register it is necessary to increment or decrement the
register after every access. (Effective Address of the Operand = Content of Register - 1 ) 23
Relative Address Mode:
• In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address.
• It results in a shorter address field in the instruction format since the relative address can
be specified with a smaller number of bits compared to the number of bits required to
designate the entire memory address.
• Effective Address = Content of Program Counter + Address part of the instruction
• Program counter (PC) always contains the address of the next instruction to be executed.
• After fetching the address of the instruction, the value of program counter immediately
increases.

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Indexed Addressing Mode:
• In this mode the content of an index register is added to the address part of the instruction
to obtain the effective address.
• The address field of the instruction defines the beginning address of a data array in
memory.
• Each operand in the array is stored in memory relative to the beginning address.
• The distance between the beginning address and the address of the operand is the index
value stored in the index register.
• Effective address of the operand is obtained by adding the content of index register with
the address part of the instruction.
• Effective Address = Content of Index Register + Address part of the instruction

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Base Register Addressing Mode:
• In this mode the content of a base register is added to the address part of the instruction
to obtain the effective address.
• This is similar to the indexed addressing mode except that the register is now called a
base register instead of an index register.
• A base register is assumed to hold a base address and the address field of the instruction
gives a displacement relative to this base address.
• Effective Address = Content of Base Register + Address part of the instruction

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 Example

XR =
Index
Register

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 Problem
A two-word instruction is stored in memory at an address designated by the symbol W.
The address field of the instruction (stored at W + 1) is designated by the symbol Y.
The operand used during the execution of the instruction is stored at an address
symbolized by Z. An index register contains the value X. State how Z is calculated
from the other addresses if the addressing mode of the instruction is
a. direct
b. indirect
c. relative
d. indexed

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 Data Transfer and Manipulation
• Computer instructions can be classified into 3 categories:
1. Data transfer instructions: Data transfer instructions cause transfer of data from one
location to another without changing the binary information content.

2. Data Manipulation Instructions: Data manipulation instructions are those that perform
arithmetic, logic, and shift operations.
• The data manipulation instructions in a typical computer are usually divided into 3 basic
types:
1. Arithmetic instructions
2. Logical & bit manipulation instructions
3. Shift instructions 29
 Arithmetic Instructions Logical and Bit Manipulation Instructions

Shift Instructions

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3. Program control instructions: Program control instructions provide decision-making
capabilities and change the path taken by the program when executed in the computer.

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 Status Bit Conditions
• It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit conditions can be stored for further analysis.
• Status bits are also called condition-code bits or flag bits.
• The four status bits are symbolized by C, S, Z, and V.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F, is 1. It is set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0's. It is cleared to 0 otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1, and
cleared to 0 otherwise.

Status register bits

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 Questions
1. An instruction is stored at location 300 with its address field at location 301 . The
address field has the value 400. A processor register R 1 contains the number 200.
Evaluate the effective address if the addressing mode of the Central Processing Unit
instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e) index with R1
as the index register.
2. Represent the following signed numbers in binary using eight bits. +83; -83; +68; -
68.
• a. Perform addition: ( -83) + (+68) in binary and interpret the result obtained.
• b. Perform subtraction: (-68) - (+83) in binary & indicate if there is an overflow.
• c. Shift binary -68 once to the right & give value of the shifted number in decimal.
• d. Shift binary -83 once to the left and indicate if there is an overflow.
3. An 8-bit computer has a register R. Determine the values of status bits C, 5, Z, and V
(Fig. 8-8) after each of the following instructions. The initial value of register R in each
case is hexadecimal 72. The numbers below are also in hexadecimal.
a. Add immediate operand C6 to R.
b. Add immediate operand 1 E t o R.
c. Subtract immediate operand 9A from R.
d. AND immediate operand 8 0 t o R. e. Exclusive-OR R with R.
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4. The program in a computer compares 2 unsigned numbers A and B by performing
a subtraction A - B & updating the status bits. Let A = 01000001 & B = 10000100.
a. Evaluate the difference and interpret the binary result.
b. Determine the values of status bits C (borrow) and Z.

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 Types of Interrupts
1. External interrupts:
• External interrupts come from input output (I/0) devices.
• Example: From external sources like a timing device, a circuit monitoring the power
supply, etc.
2. Internal interrupts:
• Internal interrupts arise from illegal or erroneous use of an instruction or data.
• Internal interrupts are also called traps. Interrupts caused by internal error conditions.
• Example: Register overflow, Attempt to divide by zero, An invalid operation code, Stack
overflow etc.
3. Software interrupts:
• External & internal interrupts are initiated from signals that occur in the hardware of the
CPU. A software interrupt is initiated by executing an instruction.
• Software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call.
• It can be used by the programmer to initiate an interrupt procedure at any desired point in
the program.

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 Addition & Subtraction Algorithm
• Representation of negative fixed-point binary numbers:
• signed-magnitude
• signed-1’s complement
• signed-2’s complement (most commonly used)
• Algorithm: Finite number of defined procedural steps for any problem.
• Flow Chart: Suitable method for presenting an algorithm.

Addition & Subtraction with Signed-Magnitude Data

Eight Different conditions for addition and subtraction

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 Addition (subtraction) algorithm
Considering 2 numbers with magnitude A and B

• When the signs of A and B are identical(different), add the 2 magnitudes & attach the sign
of A to the result.
• When the signs of A and B are different (identical), compare the magnitudes subtract the
smaller number from the larger. Choose the sign of the result to be the same as A if A > B
or the complement of the sign of A if A < B.
• If the 2 magnitudes are equal, subtract B from A & make the sign of the result positive.

Hardware Implementation

37
38
 Multiplication Algorithms
Hardware Implementation for Signed-Magnitude Data

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40
Booth Multiplication Algorithm

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42
• As in all multiplication schemes, Booth algorithm requires examination of the multiplier
bits and shifting of the partial product. Prior to the shifting, the multiplicand may be
added to the partial product, subtracted from the partial product, or left unchanged
according to the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1's in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 (provided
that there was a previous 1) in a string of O's in the multiplier.
3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.
Hardware for Booth Algorithm

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Booth algorithm for multiplication of signed 2’s complement

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Example

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Division Algorithm

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