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Processor Organization (Part 2)

Processor Organization (Part 2)

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15 views42 pages

Processor Organization (Part 2)

Processor Organization (Part 2)

Uploaded by

sarahmae.luig
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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PROCESSOR

ORGANIZATION
Instruction Interpretation and Sequencing
1. Straight line sequencing
2. Branch Instruction
Processor
Organization
Register Transfers
Register Transfers
Register
Transfers
Micro Operations
Micro-operation includes
2. Fetching a Word from Memory
2. Fetching a Word from Memory
2. Fetching a Word from Memory
3. Storing A Word In Memory
3. Storing A Word In Memory
Execution of a Complete Instruction
Execution of a Complete Instruction
Execution of Branch Instructions
Execution of Branch Instructions
Execution of Branch Instructions
EXAMPLE
SEATWORK
1. Write the control sequence and micro-
program for the instruction SUB R3, R4,
including the instruction fetch phase.
(Assume single bus architecture.)

2. Write the control sequence and micro-


program for the instruction MOVE R1, R2,
including the instruction fetch phase.
(Assume single bus architecture.)
What is Pipelining?
How Pipeline Works?
Example
Consider a water bottle packaging plant. For this
case, let there be 3 processes that a bottle
should go through, preparing the bottle(I), Filling
water in the bottle(F), Sealing the bottle(S).
We will label these stages as stage 1, stage 2,
and stage 3. Each stage take 1 minute to
complete its operation.
Example
In a non-pipelined operation, a bottle is first
prepared, and after 1 minute it is moved to stage
2 where water is filled. Now, in stage 1 nothing is
happening. Likewise, when the bottle is in stage
3 both stage 1 and stage 2 are inactive.
s1 s2 s3 s1 s2 s3 s1 s2 s3 9 mins
3 cycle
I F S
I F S 3 mins
overall
I F S
Example
In pipelined operation, when the bottle is in stage 2, the bottle
in stage 1 can be reloaded. In the same way, during the bottle 3
there could be one bottle in the 1st and 2nd stage accordingly.
Therefore at the end of stage 3, we receive a new bottle for
every minute. Hence, the average time taken to manufacture 1
bottle is:
s1 s2 s3 5 mins
I F S 3 cycle
I F S 1.67 mins
I F S overall
Pipelined operation increases the efficiency of a system.
Without pipelining
s1 s2 s3 s1 s2 s3 s1 s2 s3 9 mins
3 cycle
I F S
I F S 3 mins
overall
I F S

With pipelining
s1 s2 s3 5 mins
I F S 3 cycle
I F S 1.67 mins
I F S overall
Design of a basic Pipeline
• In a pipelined processor, a pipeline has two ends, the input end
and the output end. Between these ends, there are multiple
stages/segments such that the output of one stage is
connected to the input of the next stage and each stage
performs a specific operation.
• Interface registers are used to hold the intermediate output
between two stages. These interface registers are also called
latch or buffer.
• All the stages in the pipeline along with the interface registers
are controlled by a common clock.
Design of a basic Pipeline
• Execution sequence of
instructions in a pipelined
processor can be visualized
using a space-time diagram.
For example, consider a
processor having 4 stages and
let there be 2 instructions to be
executed. We can visualize the
execution sequence through
the following space-time
diagrams:
Design of a basic Pipeline
• Total time = 5 Cycle
Pipeline Stages
RISC processor has 5 stage instruction pipeline to execute
all the instructions in the RISC instruction set. Following are
the 5 stages of the RISC pipeline with their respective
operations:
• Stage 1 – IF (Instruction Fetch)
• Stage 2 – ID (Instruction Decode)
• Stage 3 – EX (Instruction Execute)
• Stage 4 – MEM (Memory Access)
• Stage 5 – WB (Write Back)
Pipeline Stages
• Stage 1 – IF (Instruction Fetch): In this stage the
CPU fetches the instructions from the address
present in the memory location whose value is
stored in the program counter.
• Stage 2 – ID (Instruction Decode): In this stage,
the instruction is decoded and register file is
accessed to obtain the values of registers used in
the instruction.
Pipeline Stages
• Stage 3 – EX (Instruction Execute): In this stage
some of activities are done such as ALU operations.
• Stage 4 – MEM (Memory Access): In this stage,
memory operands are read and written from/to the
memory that is present in the instruction.
• Stage 5 – WB (Write Back): In this stage,
computed/fetched value is written back to the
register present in the instructions.
Pipeline Stages
• Stage 3 – EX (Instruction Execute): In this stage
some of activities are done such as ALU operations.
• Stage 4 – MEM (Memory Access): In this stage,
memory operands are read and written from/to the
memory that is present in the instruction.
• Stage 5 – WB (Write Back): In this stage,
computed/fetched value is written back to the
register present in the instructions.
Pipeline Stages
Execution time of a pipelined process

• ETpipeline is the execution time for a pipelined process.


• k represents the number of pipeline stages.
• n is the number of tasks (or instructions) to be executed.
• Tp is the clock period or the time taken for one pipeline
stage to complete.
Pipeline Stages
Instruction 1 2 3 4 5
/Stages
Time 1 1 1 1 1
1 IF ID EX MEM WB
2 IF ID EX MEM WB
3 IF ID EX MEM WB
4 IF ID EX MEM WB
5 IF ID EX MEM WB
ETpipeline = 9 mins
Execution time of a pipelined process

• ETnon- pipeline is the execution time for a non-pipelined


process.
• k represents the number of stages.
• n is the number of tasks (or instructions) to be executed.
• Tp is the clock period or the time taken for one pipeline
stage to complete.
Pipeline Stages
Instruction 1 2 3 4 5
/Stages

Time 1 1 1 1 1
1 IF ID EX MEM WB

2 IF ID EX MEM WB

ETpipeline = 10 mins
Exercise: Laundry Processing in Pipelining vs.
Non-Pipelining
Exercise: Laundry Processing in Pipelining vs.
Non-Pipelining

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