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Chapter 2d - Verilog HDL Module Instantiation, Task Function

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6 views

Chapter 2d - Verilog HDL Module Instantiation, Task Function

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luqmanalhakimkhalid115
Copyright
© © All Rights Reserved
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FPGA PRINCIPLES AND

APPLICATIONS
BEB27303
CHAPTER 2D: Verilog HDL Module
Instantiation, Task & Function
Module Instantiations
› A define module can be used to be include in other
module
› This including a module is known as instantiation
› Modules are instantiated inside other modules, and
each instantiation creates a unique object from the
template
› Two types of instantiations - passing parameters
between the top module and lower level modules:
• Position (declarations are in the same order)
• Named (both declarations are listed and linked
Module Instantiations
› Connection by
position
• placing the ports
in exactly the
same positions in
the port lists of
both the template
and the instance
Module Instantiations
› Connection by name
• using a dot(.)
“ .template_port_nam
e
(name_of_wire_conne
cted_to_port)”.
Module Instantiations
module top ( input in1, in2, in3, in4, output out1, out2 );
dostuff first (in1, in2, out1); // Position instantiation -
must be in same order
dostuff second (.stin1(in3), .stin2(in4), .stout(out2)); //
Named instantiation - they don’t need to be in order
endmodule
module dostuff ( input stin1, stin2, output stout );
assign stout = stin1 & stin2;
endmodule
Module Instantiations
› Example 1: define a half adder to create a full adder
// Half Adder
module halfadd ( input a, b, output s, co );
assign s = a ^ b;
assign co = a & b;
endmodule

› Some wires and a couple of instantiations need to be


used to instantiate half adder to become full adder
Module Instantiations
// Full Adder from Half Adders
module fulladd ( input a, b, c_in, output sum_out,
c_out);
wire s1, c1, c2;
halfadd (a, b, s1, c1);
halfadd (s1, c_in, sum_out, c2);
assign c_out = c1 | c2;
endmodule
Module Instantiations
› Example 2: 4 bit adder module from a full adder
module

module fulladd (Cin, x, y, s, Cout);


inputCin, x, y;
outputs, Cout;
assigns = x ^ y ^ Cin,
assignCout = (x & y) | (x & Cin) | (y & Cin);
endmodule
Module Instantiations
› Instantiation rules:
• Begin with the name of the module
• Then, instance name
• Signal names in module adder4 are listed in the
right order
• Two modules may be in the same file, or in
different files with `include
Module Instantiations
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0,
s3, s2, s1, s0, carryout);
inputcarryin, x3, x2, x1, x0, y3, y2, y1, y0;
outputs3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule
Tasks
› Task are defined in the module which they are used and
can include timing delays, like posedge, negedge, #
delay
› Task can have any number of inputs and outputs.
› The variables declared within the task are local to that
task. The order of declaration within the task defines
how the variables passed to the task by the caller are
used
› Task can call another task or function used for modeling
both combinational and sequential logic
› A task must be specifically called with a statement, it
cannot be used within an expression
Tasks
› Task syntax:
• task begins with keyword task and end's with
keyword endtask
• input and output are declared after the keyword
task
• local variables are declared after input and output
declaration
Tasks
› Example: Simple task (stored in a file called
mytask.v)
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32)
end
endtask
Tasks
› Calling a task
module temp_cal (temp_a, temp_b, temp_c, temp_d);
input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v"
always @ (temp_a)
convert (temp_a, temp_b);
Tasks
always @ (temp_c)
convert (temp_c, temp_d);
endmodule

› Advantage of coding task in separate file is that, it


can be used in multiple module's.
Function
› Function are defined in the module in which they are
used and can not include timing delays, like posedge,
negedge, #delay (should be executed in "zero"
timedelay)
› Function can have any number of inputs and but only one
output
› The variables declared within the function are local to
that function. The order of declaration within the function
defines how the variables passed to the function by the
caller are used
› Function can be used for modeling combinational logic
› Function can call other functions, but can not call task
Function
› Function syntax:
• Function begins with keyword function and end's
with keyword endfunction
• Input are declared after the keyword function.
• Outputs are declared
Function
› Example: Simple function (stored in a file called
myfunction.v)
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
Function
› Calling a function
module func_test(a, b, c, d, e, f);
input a, b, c, d, e ;
output f;
wire f;
`include "myfunction.v"
assign f = (myfunction (a,b,c,d)) ? e :0;
endmodule
Summary of Task & Function
› Must be defined in a module and are local to the
module
› Task are used for common code that contains
delays, timing, event constructs, or multiple outputs
› Functions are used for purely combinational, one
output functionality
› They can have local variables, registers, but not
wires
› They can not contain always blocks
Comparison of Tasks & Function

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