Unit 3

Register Transfer and Micro

operations
 Register Transfer Language
• A digital computer system exhibits an
interconnection of digital modules such as
registers, decoders, arithmetic elements, and
Control logic.
• These digital modules are interconnected with
some common data and control paths to form a
complete digital system.
• The Register Transfer Language is the symbolic
representation of notations used to specify the
sequence of micro-operations.
The internal hardware organization of a digital
system is best defined by specifying:
• The set of registers and the flow of data
between them.
• The sequence of micro-operations performed on
the data which are stored in the registers.
• The control paths that initiates the sequence of
micro-operation
 Register Transfer
• The term Register Transfer refers to the availability of hardware
logic circuits that can perform a given micro-operation and
transfer the result of the operation to the same or another
register.
Most of the standard notations used for specifying operations on
various registers are stated below.
• The memory address register is designated by MAR.
• Program Counter PC holds the next instruction's address.
• Instruction Register IR holds the instruction being executed.
• R1 (Processor Register).
• We can also indicate individual bits by placing them in
parenthesis. For instance, PC (8-15), R2 (5), etc.
• R2 ← R1
• The following image shows the block diagram
that depicts the transfer of data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the
register R1 are connected to the 'n' inputs of register R2.
 Bus and Memory Transfers
• A bus structure, on the other hand, is more
efficient for transferring information between
registers in a multi-register configuration system.
• A bus consists of a set of common lines, one for
each bit of register, through which binary
information is transferred one at a time.
• Control signals determine which register is
selected by the bus during a particular register
transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).
• A bus system can also be constructed using three-state
gates instead of multiplexers.
• The three state gates can be considered as a digital
circuit that has three gates are
• 1 and 0 as in a conventional gate
• The Third one is high impedance
The most commonly used three state gates in case of the
bus system is a buffer gate.
• The outputs generated by the four buffers are connected to form a single bus line.
• Only one buffer can be in active state at a given point of time.
• The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
• A 2 * 4 decoder ensures that no more than one control input is active at any given point
of time.
Memory Transfer:
• Most of the standard notations used for specifying operations
on memory transfer are stated below.
• The transfer of information from a memory unit to the user
end is called a Read operation.
• The transfer of new information to be stored in the memory
is called a Write operation.
• A memory word is designated by the letter M.
• We must specify the address of memory
word while writing the memory transfer
operations.
• The address register is designated by
AR and the data register by DR.
• Thus, a read operation can be stated as:
• Read: DR ← M [AR]
• Write: M [AR] ← R1
 Arithmetic Micro-operations
• The operations performed on the data stored in
registers are known as micro operations. Micro
operations are classified into the following types:
1. Arithmetic micro operations
2. Logic Micro operations
3. Shift micro operations
Arithmetic micro operations:
• The basic Arithmetic Micro-operations are classified in
the following categories:
• Addition Symbolic Representation Description

• Subtraction R3 ← R1 + R2
The contents of R1 plus R2 are
• Increment transferred to R3.
R3 ← R1 - R2 The contents of R1 minus R2 are
• Decrement transferred to R3.
R2 ← R2' Complement the contents of R2 (1's
• Shift complement)
R2 ← R2' + 1 2's complement the contents of R2
(negate)
R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2
(subtraction)
R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Binary Adder:
• A Binary Adder is a digital circuit that performs the arithmetic
sum of two binary numbers provided with any length.
• A Binary Adder is constructed using full-adder circuits connected
in series, with the output carry from one full-adder connected to
the input carry of the next full-adder.
• The augend bits (A) and the addend bits (B) are designated by
subscript numbers from right to left, with subscript '0' denoting
the low-order bit.
• The carry inputs starts from C0 to C3 connected in a chain
through the full-adders. C4 is the resultant output carry generated
by the last full-adder circuit.
• The output carry from each full-adder is connected to the input
carry of the next-high-order full-adder.
• The sum outputs (S0 to S3) generates the required arithmetic sum
of augend and addend bits.
• The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source
register R1 and data bits for B input comes from source register
R2.
• The arithmetic sum of the data inputs of A and B can be
transferred to a third register or to one of the source registers (R1
or R2).
Binary Adder-Subtractor:
• The Subtraction micro-operation can be done easily by taking the
2's compliment of addend bits and adding it to the augend bits.
• The Arithmetic micro-operations like addition and subtraction can
be combined into one common circuit by including an exclusive-
OR gate with each full adder.
• When the mode input (M) is at a low logic, i.e. '0', the
circuit act as an adder and when the mode input is at a
high logic, i.e. '1', the circuit act as a subtractor.
• The exclusive-OR gate connected in series receives input
M and one of the inputs B.
• When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is
0, and the circuit performs A plus B.
• When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added
through the input carry. The circuit performs the
operation A plus the 2's complement of B.
 Binary Incrementer
• The increment micro-operation adds one binary value to the
value of binary variables stored in a register.
• For instance, a 4-bit register has a binary value 0110, when
incremented by one the value becomes 0111.
• The increment micro-operation is best implemented by a 4-
bit combinational circuit incrementer.
• A logic-1 is applied to one of the inputs of least
significant half-adder, and the other input is
connected to the least significant bit of the
number to be incremented.
• The output carry from one half-adder is
connected to one of the inputs of the next-
higher-order half-adder.
• The binary incrementer circuit receives the four
bits from A0 through A3, adds one to it, and
generates the incremented output in S0 through
S3.
• The output carry C4 will be 1 only after
incrementing binary 1111.
 Logic Micro-Operations

• Logic micro operations specify binary

operations for strings of bits stored in
registers.
These operations consider each bit of the
register separately and treat them as binary
variables.
• There are 16 different logic operations that can
be performed with two binary variables.
• Hardware Implementation of Logic Micro
operations:
Shift Micro operations:
• Shift micro operations are used for serial
transfer of data. They are also used in
conjunction with arithmetic, logic, and other
data-processing operations.
• During a shift-left operation the serial input
transfers a bit into the rightmost position.
• During a shift-right operation the serial input
transfers a bit into the leftmost position
• There are three types of shifts: logical, circular,
and arithmetic.
A logical shift is one that transfers 0 through the
serial input. We will adopt the symbols shl and
shr for logical shift-left and shift-right
microoperations. For example:

R1 ← shl R1
R2 &arr; shr R2
• Arithmetic shifts must leave the sign bit
unchanged because the sign of the number
remains the same

• when it is multiplied or divided by 2. The

leftmost bit in a register holds the sign bit, and
the remaining bits hold the number. The sign bit
is 0 for positive and I for negative. Negative
numbers are in 2's complement form.
Hardware Implementation:
• A possible choice for a shift unit would be a bidirectional shift
register with parallel load
• Information can be transferred to the register in parallel and then
shifted to the right or left.
• In this type of configuration, a clock pulse is needed for loading
the data into the register, and another pulse is needed to initiate
the shift.
• In a processor unit with many registers it is more efficient to
implement the shift operation with a combinational circuit.
• In this way the content of a register that has to be shifted is first
placed onto a common bus whose output is connected to the
combinational shifter, and the shifted number is then loaded back
into the register.
• This requires only one clock pulse for loading the shifted value into
the register.
 Arithmetic Logic Shift Unit
• Instead of having individual registers performing the micro operations directly,
computer systems employ a number of storage registers connected to a
common operational unit called an arithmetic logic unit, abbreviated ALU.
• To perform a micro operation, the contents of specified registers are placed in
the inputs of the common ALU.
• The ALU performs an operation and the result of the operation is then
transferred to a destination register.
• The ALU is a combinational circuit so that the entire register transfer operation
from the source registers through the ALU and into the destination register can
be performed during one clock pulse period.
• The shift micro operations are often performed in a seperate unit, but
sometimes the shift unit is made part of the ALU.
• The arithmetic, logic, and shift circuits introduced in previous sections can be
combined into one ALU with common selection variables.
• One stage of an arithmetic logic shift unit is shown in Fig. below. The subscript
i designates a typical stage.
• Inputs Ai and Bi are applied to both the arithmetic and logic
 Micro programmed control unit
• A control unit whose binary control variables
are stored in memory is called a micro
programmed control unit.
• Dynamic microprogramming: A more advanced
development known as dynamic microprogramming
permits a micro program to be loaded initially from
an auxiliary memory such as a magnetic disk. Control
units that use dynamic microprogramming employ a
writable control memory. This type of memory can be
used for writing
• Control Memory: A computer that employs a
micro programmed control unit will have two
separate memories:
• A main memory
• A control memory
Micro operation, Microinstruction, Micro program,
Microcode:
• Micro operations: In computer central processing
units, micro-operations (also known as a micro-ops)
are detailed low-level instructions used in some
designs to implement complex machine instructions
(sometimes termed macro-instructions in this context).
• Micro instruction: A symbolic micro program can be
translated into its binary equivalent by means of an
assembler.
• Each line of the assembly language micro program
defines a symbolic microinstruction.
• Each symbolic microinstruction is divided into five
fields: label, micro operations, CD, BR, and AD.
Micro program: A sequence of microinstructions constitutes a micro
program.
• Since alterations of the micro program are not needed once the control
unit is in operation, the control memory can be a read-only memory
(ROM).
• ROM words are made permanent during the hardware production of the
unit.
• The use of a micro program involves placing all control variables in words
of ROM for use by the control unit through successive read operations.
• The content of the word in ROM at a given address specifies a
microinstruction.
Microcode:
• Microinstructions can be saved by employing subroutines that use
common sections of microcode.
• For example, the sequence of micro operations needed to generate the
effective address of the operand for an instruction is common to all
memory reference instructions.
• This sequence could be a subroutine that is called from within many other
routines to execute the effective address computation.
Organization of micro programmed control unit:
• The control memory is assumed to be a ROM,
within which all control information is
permanently stored.
The microinstruction address is specified in the control
memory address register.
• All the control information is saved in the control memory,
which is considered to be a ROM.
• The microinstruction received from memory is stored in the
control register.
• A control word in the microinstruction specifies one or
multiple micro-operations for a data processor.
• The next address is calculated in the circuit of the next
address generator and then transferred to the control
address register for reading the next microinstruction when
the micro-operations are being executed.
• Because it determines the sequence of addresses received
from control memory, the next address generator is also
known as a micro program sequencer.
 Address Sequencing
• Microinstructions are stored in control
memory in groups, with each group specifying
a routine.
• To appreciate the address sequencing in a
micro-program control unit, let us specify the
steps that the control must undergo during
the execution of a single computer instruction.
Step-1: An initial address is loaded into the control
address register when power is turned on in the
computer.
• This address is usually the address of the first
microinstruction that activates the instruction
fetch routine.
• The fetch routine may be sequenced by
incrementing the control address register
through the rest of its microinstructions.
• At the end of the fetch routine, the instruction is
in the instruction register of the computer.
Step-2: The control memory next must go through
the routine that determines the effective address
of the operand.
• A machine instruction may have bits that specify
various addressing modes, such as indirect
address and index registers.
• The effective address computation routine in
control memory can be reached through a
branch microinstruction, which is conditioned on
the status of the mode bits of the instruction.
• When the effective address computation routine
is completed, the address of the operand is
available in the memory address register.
Step-3: The next step is to generate the micro
operations that execute the instruction fetched from
memory.
• The micro operation steps to be generated in
processor registers depend on the operation code
part of the instruction.
• Each instruction has its own micro-program routine
stored in a given location of control memory.
• The transformation from the instruction code bits
to an address in control memory where the routine
is located is referred to as a mapping process.
• A mapping procedure is a rule that transforms the
instruction code into a control memory address
Step-4: Once the required routine is reached, the
microinstructions that execute the instruction may be
sequenced by incrementing the control address
register.
• Micro-programs that employ subroutines will require
an external register for storing the return address.
• Return addresses cannot be stored in ROM because
the unit has no writing capability.
• When the execution of the instruction is completed,
control must return to the fetch routine.
• This is accomplished by executing an unconditional
branch microinstruction to the first address of the
fetch routine.
INPUT OUTPUT

Chapter 8
 Input output Organisation
• Input-Output Interface is used as an
method which helps in transferring of
information between the internal
storage devices i.e. memory and the
external peripheral device
• A peripheral device is that which
provide input and output for the
computer, it is also called Input-
Output devices.
 Input output Interface
• In computer system, there are special
hardware components between the CPU and
peripherals to control or manage the input-
output transfers.
• These components are called input-output
interface units because they provide
communication links between processor bus
and peripherals.
• They provide a method for transferring
information between internal system and
input-output devices.
 IO Bus and interface Modules

• A typical communication link between the processor and

several peripherals
• The 1/0 bus consists of data lines, address lines, and
control lines.
• The magnetic disk, printer, and terminal are employed in
practically any general-purpose computer.
• The magnetic tape is used in some computers for backup
storage
• Each peripheral device has associated with it an interface
unit. Each interface decodes the address and control
received from the UO bus, interprets them for the
peripheral, and provides signals for the peripheral
controller
• The IO bus from the processor is attached to all
peripheral interfaces.
• To communicate with a particular device, the processor
places a device address on the address lines
• IO Command: The interface selected responds to a
function and proceeds to execute it.
• Control Command: A control command is issued to
activate the peripheral and to inform it what to do.
Ex: to rewind the tape, or to start the tape moving in the
forward direction
• Status
• Output data
• Input data
• Status: A status command is used to test various
status conditions in the interface and the
peripheral.
Ex: For example, the computer may wish to check
the status of the peripheral before a transfer is
initiated
• Output data: A data output command causes the
interface to respond by transferring data from the
bus into one of its registers.
• Input data: The data input command is the
opposite of the data output. In this case the
interface receives an item of data from the
peripheral and places it in its buffer register.
• IO Versus Memory Bus: In addition to
communicating with I/O, the processor must
communicate with the memory unit.
• There are three ways that computer buses can
be used to communicate with memory and I/O:
1. Use two separate buses, one for memory and
the other for I/O.
2. Use one common bus for both memory and I/O
but have separate control lines for each.
3. Use one common bus for memory and I/O with
common control lines.
Example of I/O interface unit
 Modes of Transfer
• . Information transferred from the central computer into an
external device originates in the memory unit
• The CPU merely executes the 110 instructions and may accept
the data temporarily, but the ultimate source or destination is
the memory unit.
• Data transfer between the central computer and 110 devices
may be handled in a variety of modes.
• Data transfer to and from peripherals may be handled in one of
three possible modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
Programmed I/O:
• Programmed I/O operations are the result of
I/O instructions written in the computer
program. Each data item transfer is initiated by
an instruction in the program.
• Once a data transfer is initiated, the CPU is
required to monitor the interface to see when a
transfer can again be made.
Interrupted I/O:
• In the programmed I/O method, the CPU stays in
a program loop until the I/O unit indicates that it
is ready for data transfer. This is a time-
consuming process since it keeps the processor
busy needlessly
• It can be avoided by using an interrupt facility
and special commands to inform the interface to
issue an interrupt request signal when the data
are available from the device.
• In the meantime the CPU can proceed to execute
another program.
DMA:
• Transfer of data under programmed 110 is between
CPU and peripheral. In direct memory access (DMA),
the interface transfers data into and out of the
memory unit through the memory bus.
• The CPU merely delays its memory access operation to
allow the direct memory 110 transfer.
IOP:
• Many computers combine the interface logic with the
requirements for direct memory access into one unit
and call it an I/O processor (lOP).
• The lOP can handle many peripherals through a DMA
and interrupt facility.
• Example of Programmed I/O:
• Flow chart:
 Direct Memory Access(DMA)
• The transfer of data between a fast storage
device such as magnetic disk and memory is
often limited by the speed of the CPU
 Why is DMA?
• It is wasteful to feed data into a controller
register 1 bytes at a time. (PIO)
• The DMA unit is word.
• In the high loading environment, a system
with DMA has better improvement.
 DMA transfer
1. device driver told to transfer disk
data to buffer at address X
CPU
2. device driver tells disk controller to
5. DMA controller transfers bytes transfer C bytes fromdisk to buffer at
to buffer X, increasing memory address X
address and decreasing C until C=0 cache
6. when C=0, DMA interrupts CPU
to signal transfer completion DMA/bus/ X
interrupt CPU memory bus Memory buffer
controller

PCI bus

3. disk controller initiates

IDE disk DMA transfer
controller 4. disk controller sends each
byte to DMA controller

disk disk

disk disk
 DMA Progress
• To initiate a DMA transfer, the host writes a
DMA command into memory:
– A pointer to the source of a transfer
– A count of the number of bytes to be transferred
– ……..
• The CPU writes the address of the DMA
command block to the DMA controller.
 DMA Progress (cont.)
• The DMA controller proceeds to operate the
memory bus directly without CPU help.
• Handshaking exists between DMA controller
and device controller.
• When the entire transfer is finished, the DMA
controller will interrupts the CPU.
 Handshaking
• DMA-request and DMA_acknowledge
– When a word of data is available, the device
controller places a signal on the DMA-request
wire.
– The signal causes the DMA controller to seize the
memory bus,
• To place the desired address on the memory-address
wire
• To place a signal on the DMA-acknowledge wire
 Handshaking (cont.)
• When the device controller receives the DMA-
acknowledge signal,
– it transfer the word of data to memory
– and remove the DMA_request signal.
• The communication between the lOP and the
devices attached to it is similar to the program
control method of transfer.
• Communication with the memory is similar to
the direct memory access method.
• The way by which the CPU and lOP
communicate depends on the level of
sophistication included in the system.
• In very-large-scale computers, each processor
is independent of all others and any one
processor can initiate an operation.
• CPU-lOP Communication:
The communication between CPU and lOP may
take different forms, depending on the particular
computer considered.
In most cases the memory unit acts as a message
center where each processor leaves information
for the other.
To appreciate the operation of a typical lOP, we
will illustrate by a specific example the method by
which the CPU and lOP communicate
 DMA Controller
• DMA Controller is a type of control unit that
works as an interface for the data bus and
the I/O Devices.
• DMA Controller has the work of transferring
the data without the intervention of the
processors, processors can control the data
transfer.
• DMA Controller also contains an address
unit, which generates the address and
selects an I/O device for the transfer of data.
 Working of DMA Controller

• The DMA controller registers have

three registers as follows.
• Address register – It contains the
address to specify the desired
location in memory.
• Word count register – It contains
the number of words to be
transferred.
• Control register – It specifies the
transfer mode.
Explanation: The CPU initializes the
DMA by sending the given information
through the data bus.
• The starting address of the memory
block where the data is available (to
read) or where data are to be stored (to
write).
• It also sends word count which is the
number of words in the memory block
to be read or written.
• Control to define the mode of transfer
such as read or write.
• A control to begin the DMA transfer
 Modes of Data Transfer in DMA
There are 3 modes of data transfer in DMA that
are described below.
• Burst Mode: In Burst Mode, buses are handed
over to the CPU by the DMA if the whole data is
completely transferred, not before that.
• Cycle Stealing Mode: In Cycle Stealing Mode,
buses are handed over to the CPU by the DMA
after the transfer of each byte. Continuous
request for bus control is generated by this Data
Transfer Mode. It works more easily for higher-
priority tasks.
• Transparent Mode: Transparent Mode in DMA
does not require any bus in the transfer of the
data as it works when the CPU is executing the
transaction.
Applications
• The applications of DMA controller include the following,

• A DMA controller is used to generate memory addresses & begin

memory read/write cycles.
• The process of transmitting data without the processor’s
involvement is frequently used for transmitting data from input to
output devices.
• This is a hardware device used to allow I/O devices to access
memory directly with less involvement of the processor.
• The data transmission can be done at the fastest rate by using
DMA.
• The DMA device performs like a bus master to read & write
physical memory.
• This device is mainly used to offload the software & processors
from copying large data from one place to another within memory
 Instruction level parallelism
• Instruction-level parallelism (ILP) is a measure
of how many of the operations in a computer
program can be performed simultaneously.
The potential overlap among instructions is
called instruction level parallelism.
Two approaches to exploiting ILP are:
• Static Technique which is software dependent
• Dynamic Technique which is hardware
dependent
A Hazard id created whenever there is dependency between instructions.