Unit 2

Basic Computer
Organisation and Design
 INSTRUCTION CODES

COMPUTER REGISTERS

COMPUTER INSTRUCTIONS

TIMING AND CONTROL

INSTRUCTION
CYCLE

2
 Instruction Codes
◉ The organization of the computer is defined by its internal registers,
timing and control structures, and the sets of instructions it uses.
◉ The internal organization of a digital system is defined by the sequence of
micro-operations it performs on data stored in its registers.
◉ The general purpose computer is capable of executing various micro-
operations and can be instructed as to what specific sequence of
operations it must perform. The user of a computer can control the process
by means of a program.

3
◉ Program: set of instructions that specify the operations, operands, and the
sequence by which processing has to occur.
◉ Instruction: a binary code that specifies a sequence of micro-operations for
the computer.
The computer reads each instruction from memory and places it in a
control register. The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a sequence of micro-
operations. – Instruction Cycle
◉ Instruction Code: group of bits that instruct the computer to perform
specific operation.
◉ Instruction code is usually divided into two parts:
Opcode and address(operand)

4
◉ Operation Code (opcode):
group of bits that define the operation
Eg: add, subtract, multiply, shift, complement.
No. of bits required for opcode depends on no. of operations available
in computer.
n bit opcode >= 2n (or less) operations
◉ Address (operand):
specifies the location of operands (registers or memory words)
Memory words are specified by their address
Registers are specified by their k-bit binary code
k-bit address >= 2k registers

5
 Stored Program Organization
◉ The ability to store and execute instructions is the most important property of a general-purpose computer
◉ The simplest way to organize a computer is to have one processor register and an instruction code format
with two parts.
◉ The first part specifies the operation to be performed
and the second specifies an address.
◉ The memory address tells the control where to find
an operand in memory.
This operand is read from memory and used as the data
to be operated on together with the data stored
in the processor register. That type of stored program
concept is called stored program organization.

6
 Direct and Indirect address Modes

◉ In direct addressing mode, the actual address of the data is mentioned in

the instructions itself.
◉ On the other hand, indirect addressing mode contains the effective address
of the memory location where the actual address of the data resides.
◉ The direct addressing mode is also known as the absolute addressing
mode.
◉ The effective address refers to the address of an exact memory location in
which an operand’s value is actually present.

7
8
 Computer Registers

What is the need for computer registers?

9
10
 Common Bus System

◉ The basic computer has eight registers, a memory unit, and a control unit
◉ Paths must be provided to transfer information from one register to another
and between memory and registers.
◉ A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
◉ The outputs of seven registers and memory are connected to the common
bus

11
12
 Computer Instructions

◉ The basic computer has three instruction code formats

Memory Reference Instructions
Register Reference Instructions
Input Output Instruction

13
14
Instruction Set Completeness:
The set of instructions are said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:
◉ Arithmetic, logical, and shift instructions
◉ Data Instructions (for moving information to and from memory and
processor registers)
◉ Program control instructions together with instructions that check status
conditions
◉ Input and output instructions

15
 Timing and Control

◉ The timing for all registers in the basic computer is controlled by a master
clock generator.
◉ The clock pulses are applied to all flip-flops and registers in the system,
including the flip-flops and registers in the control unit.
◉ The clock pulses do not change the state of a register unless the register is
enabled by a control signal.
◉ There are two major types of control organization:
Hardwired control
Micro programmed control

16
17
Control Unit

18
◉ It consists of two decoders, a sequence counter, and a number of control
logic gates.
◉ An instruction read from memory is placed in the instruction register (IR). It
is divided into three parts: The I bit, the operation code, and bits 0 through
11.
◉ The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.
The eight outputs of the decoder are designated by the symbols D0 through
D7.
◉ Bit 15 of the instruction is transferred to a flip-flop designated by the symbol
I.
◉ Bits 0 through 11 are applied to the control logic gates.
◉ The 4-bit sequence counter can count in binary from 0 through 15

19
 Instruction cycle

A program residing in the memory unit of a computer consists of a sequence

of instructions. These instructions are executed by the processor by going
through a cycle for each instruction.
In a basic computer, each instruction cycle consists of the following phases:
◉ Fetch instruction from memory.
◉ Decode the instruction.
◉ Read the effective address from memory.
◉ Execute the instruction.

20
◉ Fetch and decode:
1. Initially the program counter PC is loaded with the address of first
instruction in the program
2. The sequence counter SC is cleared to 0 providing a decoded timing signal
T0 after each clock pulse SC is incremented by 1. so the timing signals go
through T0, T1 ,T2

21
22
◉ To provide the data path for the transfer of PC to AR we must apply timing
signal T0 to achieve the following connection:
1. Place the content of PC onto the bus by making the bus selection inputs
S0S1S2 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR .
3. The next clock transition initiates the transfer from PC to AR since T0 = 1.
4. In order to implement the second statement
T1: IR <-M[AR], PC <- PC + 1

23
◉ it is necessary to use timing signal T1 to provide the following connections
in the bus system.
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2S1S0 = 111.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC.

The next clock transition initiates the read and increment operations since
T1= 1.

24
Determine the Type of Instruction:
◉ The timing signal that is active after
the decoding is T3
◉ During time T3 the control unit
determines the type of instruction that
was just read from memory.

25
Register reference instruction:
◉ Register-reference instructions are recognized by the control
when D7 = 1 and I = 0.
◉ These instructions use bits 0 through 11 of the instruction code to specify
one of 12 instructions.
◉ These 12 bits are available in IR(0-11). They were also transferred to AR
during time T2
◉ For example, the instruction CLA has the hexadecimal code 7800, which
gives the binary equivalent 0111 1000 0000 0000

26
27
 Memory-Reference Instructions

◉ AND to AC: This is an instruction that performs the AND logic operation on
pairs of bits in AC and the memory word specified by the effective address.
◉ The result of the operation is transferred to AC.

28
◉ ADD to AC: This instruction adds the content of the memory word specified
by the effective address to the value of AC.
◉ The sum is transferred into AC and the output carry Cout is transferred to the
E (extended accumulator) flip-flop.

◉ LDA: Load to AC: This instruction transfers the memory word specified by the
effective address to AC. The rnicrooperations needed to execute this
instruction are

29
◉ STA: Store AC: This instruction stores the content of AC into the memory
word specified by the effective address. Since the output of AC is applied to
the bus and the data input of memory is connected to the bus, we can
execute this instruction with one micro operation:

◉ BUN: Branch Unconditionally: This instruction transfers the program to the

instruction specified by the effective address.
◉ The BUN instruction allows the programmer to specify an instruction out of
sequence and we say that the program branches (or jumps) unconditionally.

30
◉ BSA: Branch and Save Return Address: The BSA instruction stores the
address of the next instruction in sequence (which is available in PC) into a
memory location specified by the effective address

◉ The BSA instruction performs the following numerical operation:

◉ ISZ: Increment and Skip if Zero: This instruction increments the word
specified by the effective address, and if the incremented value is equal to 0,
PC is incremented by 1. This negative number is repeatedly incremented by
one, it eventually reaches the value of zero. At that time PC is incremented by
one in order to skip the next instruction in the program

31
◉ Control Flowchart:

32
 Input-Output and Interrupt
◉ A computer can serve no useful purpose unless it communicates with the
external environment.
◉ Commercial computers include many types of input and output devices
Input-Output Configuration

33
Input Register: The input register INPR consists of eight bits and holds an
alphanumeric input information.
The 1-bit input flag FGI is a control flip-flop.
The flag bit is set to 1 when new information is available in the input device and
is cleared to 0 when the information is accepted by the computer.
The process of information transfer is as follows.
1. Initially, the input flag FGI is cleared to 0.
2. When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted
into INPR and the input flag FGI is set to 1.
Output register: The output register OUTR works similarly but the direction of
information flow is reversed
◉ Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it
is 1, the information from AC is transferred in parallel to OUTR and FGO is
cleared to 0.
34
Input-Output Instructions :
Input and output instructions are needed for
1. Transferring information to and from AC register,
2. For checking the flag bits, and
3. For controlling the interrupt facility.

35
◉ Program Interrupt : The interrupt enable flip-flop IEN can be set and
cleared with two instructions. When IEN is cleared to 0 (with the !OF
instruction), the flags cannot interrupt the computer.
◉ When IEN is set to 1 (with the ION instruction), the computer can be
interrupted.

36
Interrupt Cycle:
◉ The interrupt cycle is a hardware implementation of a branch and save return
address operation. The return address available in PC is stored in a specific location
where it can be found later when the program returns to the instruction at which it
was interrupted.

37
38
Central Processing
Unit
39
 Introduction

◉ The part of the computer that performs the bulk of data-processing

operations is called the central processing unit and is referred to as the
CPU.

◉ The design of a CPU is a task that in large part involves choosing the
hardware for implementing the machine instructions

40
 General Register Organization

◉ Memory locations are needed for storing pointers, counters, return

addresses, temporary results, and partial products during operations.
◉ Having to refer to memory locations for such applications is time
consuming because memory access is the most time-consuming,
Operations in a computer ; more convenient and more efficient to store
these intermediate values in processor registers.

41
Bus system:
◉ A bus organization for seven CPU registers.
◉ The output of each register is connected to two multiplexers (MUX) to form
the two buses A and B.
◉ The selection lines in each multiplexer select one register or the input data
for the particular bus.

42
R1 <--R2 + R3
The control must provide binary selection
variables to the following selector inputs:
1. MUX A selector (SELA): to place the
content of R2 into bus A.
2. MUX B selector (SELB): to place the
content o f R3 into bus B.
3. ALU operation selector (OPR): to
provide the arithmetic addition A+ B.
4. Decoder destination selector (SELD): to
transfer the content of the output bus into
R1.

43
 Stack Organization

◉ A useful feature that is included in the CPU of most computers is a stack or

last-in, first-out (UFO) list
◉ A stack is a storage device that stores information in such a manner that the
item stored last is the first item retrieved
◉ The operation of a stack can be compared to a stack of trays.
◉ The last tray placed on top of the stack is the first to be taken off.
◉ The stack in digital computers is essentially a memory unit with an address
register that can count only
◉ The register that holds the address for the stack is called a stack pointer
(SP) because its value always points at the top item in the stack
◉ The two operations of a stack are the insertion and deletion of items. The
operation of insertion is called push (or push-down)
44
◉ Register Stack:
A stack can be placed in a portion of a large memory or it can be
organized as a collection of a finite number of memory words or registers

45
Push:
◉ Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0,
◉ so that SP points to the word at address 0 and the stack is marked empty and
not full.
◉ If the stack is not full (if FULL = 0), a new item is inserted with a push
operation.
◉ The push operation is implemented with the following sequence of micro
operations;

46
POP:
A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The
pop operation consists of the following sequence of microoperations:

47
Memory Stack: Stack exists can be implemented in a Random Access Memory which
is attached to CPU.
The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer

48
Reverse Polish Notation :
◉ A stack organization is very effective for evaluating arithmetic expressions.
◉ The common mathematical method of writing arithmetic expressions
imposes difficulties when evaluated by a computer.
◉ The common arithmetic expressions are written in 3 ways
1. Infix Notation
2. Prefix Notation (Polish Notation)
3. Post fix Notation(Reverse Polish Notation)

49
50
Evaluation of Arithmetic Expression:
1. Convert the expression into its equivalent Reverse polish Notation.
2. The operands are pushed into the stack
3. Once operator comes pop 2 elements from the stacks and perform the
operation

51
Evaluation of Arithmetic Expressions:

52
 Instruction Formats
◉ A collection of operation codes, as well as operands that handle the
operation codes, are included in the instruction.
◉ The bit design in an instruction is supported by the instruction format.
◉ The common fields in instruction formats are
opcode: This field specifies the operation to be performed
addressing mode: This field specifies the way the address is specified.
Address: This field designates a memory address or processor
address

53
CPU Organisation:
Most computers fall into one of the three types of CPU organisations.
◉ Single accumulator organisations
The instruction that specifies an arithmetic addition is defined by an
assembly language instruction as
ADD X
where X is the address of the operand. The ADD instruction in this case
results in the operation
AC <--AC + M [X].
◉ General Register organisations
ADD R 1 , R 2 , R3 ADD R 1 , X
ADD R 1 , R2 Rl <--R1 + M[X]
MOV R 1 , R2
54
Stack Organisation:
◉ Computers with stack organization would have PUSH and POP instructions
which require an address field.
PUSH X
The instruction
ADD in a stack computer consists of an operation code only with no address field.

55
Types of Instructions: Based on the number of address fields present in the
instruction can be classified into
1. Three address instructions
2. Two Address Instructions
3. One address instructions
4. Zero address instructions

56
◉ Three address instructions: Computers with three-address instruction
formats can use each address field to specify either a processor register or a
memory operand. X = (A + B) * (C + D)

The advantage of the three-address format is that it results in short programs when
evaluating arithmetic expressions.

57
Two-Address Instructions: Each address field can specify either a processor
register or a memory word.
X = (A + B) * (C + D)

58
One-Address Instructions : One-address instructions use an implied
accumulator (AC) register for all data manipulation
X = (A + B) * (C + D)

59
Zero-Address Instructions :
A stack-organized computer does not use an address field for the instructions
ADD and MUL. The PUSH and POP instructions, however, need an address field
to specify the operand that communicates with the stack.
X = (A + B) * (C + D)

60
 Addressing Modes

◉ The different methods/modes for specifying the operand address in the

instructions are known as addressing modes.
Types of Addressing Modes:
◉ Immediate Mode
◉ Register Mode
◉ Register indirect mode
◉ Auto increment or decrement Mode
◉ Direct Addressing mode
◉ Indirect Addressing Mode
◉ Indexed Addressing Mode
◉ Relative Addressing Mode
◉ Implied Addressing Mode
61
◉ Immediate Mode (symbol #):
In this mode data is present in address field of instruction .Designed like one
address instruction format.

● MOV AL, 35H (move the data 35H into AL register)

62
◉ Direct addressing/ Absolute addressing Mode (symbol [ ]): The
operand’s offset is given in the instruction as an 8 bit or 16 bit
displacement element. In this addressing mode the 16 bit effective address
of the data is the part of the instruction.
Here only one memory reference operation is required to access the data.

ADD AL,[0301]

63
◉ Indirect addressing Mode (symbol @ or () ):In this mode address field of
instruction contains the address of effective address. Here two references
are required.
1st reference to get effective address.
2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kind:
◉ Register Indirect: In this mode effective address is in the register, and corresponding
register name will be maintained in the address field of an instruction.
Here one register reference, one memory reference is required to access the data.
◉ Memory Indirect: In this mode effective address is in the memory, and corresponding
memory address will be maintained in the address field of an instruction.
Here two memory reference is required to access the data.

64
◉ Indexed addressing mode: The operand’s offset is the sum of the content
of an index register SI or DI and an 8 bit or 16 bit displacement.
Example:MOV AX, [SI +05]
◉ Register mode: In register addressing the operand is placed in one of 8 bit
or 16 bit general purpose registers. The data is in the register that is
specified by the instruction.
Here one register reference is required to access the data.

65
◉ Register Indirect mode: In this addressing the operand’s offset is placed in
any one of the registers BX,BP,SI,DI as specified in the instruction. The
effective address of the data is in the base register or an index register that is
specified by the instruction.
Here two register reference is required to access the data.

66
◉ Auto Indexed (increment mode): Effective address of the operand is the
contents of a register specified in the instruction. After accessing the
operand, the contents of this register are automatically incremented to
point to the next consecutive memory location.(R1)+.
Here one register reference,one memory reference and one ALU operation is
required to access the data.
Example:Add R1, (R2)+
// OR R1 = R1 +M[R2]
R2 = R2 + d

67
◉ Auto indexed ( decrement mode): Effective address of the operand is the
contents of a register specified in the instruction. Before accessing the
operand, the contents of this register are automatically decremented to
point to the previous consecutive memory location. –(R1)
Here one register reference,one memory reference and one ALU operation is
required to access the data.
Example:
Add R1,-(R2)
//OR R2 = R2-d
R1 = R1 + M[R2]

68
◉ Relative Addressing Mode:
In this mode, the Effective Address (EA) of the operand is calculated by
adding the content of the CPU register and the address part of the instruction
word. The effective address is calculated by adding displacement (immediate
value given in the instruction) and the register value.

69
 Data Manipulation Instructions

◉ Data manipulation instructions perform operations on data and provide

computational capabilities for the computer. The data manipulation
instructions in a typical computer are usually divided into three basic types
as follows.
Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions

70
◉ Arithmetic instructions:
The four basic operations are addition, subtraction, multiplication, and
division. Most computers provide instructions for all four operations. Typical
Arithmetic Instructions –

71
 Mnemon
Name Example Explanation
ic
It will increment the register B by 1
Increment INC INC B
B<-B+1
It will decrement the register B by 1
Decrement DEC DEC B
B<-B-1
It will add contents of register B to the contents of the accumulator
Add ADD ADD B and store the result in the accumulator
AC<-AC+B
It will subtract the contents of register B from the contents of the
Subtract SUB SUB B accumulator and store the result in the accumulator
AC<-AC-B

It will multiply the contents of register B with the contents of the

Multiply MUL MUL B accumulator and store the result in the accumulator
AC<-AC*B

It will divide the contents of register B with the contents of the

Divide DIV DIV B accumulator and store the quotient in the accumulator
AC<-AC/B
It will add the contents of register B and the carry flag with the
Add with contents of the accumulator and store the result in the
ADDC ADDC B
carry accumulator
AC<-AC+B+Carry flag
It will subtract the contents of register B and the carry flag from
Subtract with the contents of the accumulator and store the result in the
SUBB SUBB B
borrow accumulator
AC<-AC-B-Carry flag
It will negate a value by finding 2’s complement of its single operand.
Negate(2’s
NEG NEG B This means simply operand by -1.
complement)
B<-B’+1
72
◉ Logical and Bit Manipulation Instructions: Logical instructions perform binary operations on
strings of bits stored in registers. They are helpful for manipulating individual bits or a group of
bits. Typical Logical and Bit Manipulation
Name Mnemonic Example Explanation
It will set the accumulator to 0
Clear CLR CLR
AC<-0
It will complement the accumulator
Complement COM COM A
AC<-(AC)’
It will AND the contents of register B with the contents of accumulator and store
AND AND AND B it in the accumulator
AC<-AC AND B
It will OR the contents of register B with the contents of accumulator and store it
OR OR OR B in the accumulator
AC<-AC OR B
It will XOR the contents of register B with the contents of the accumulator and
Exclusive-OR XOR XOR B store it in the accumulator
AC<-AC XOR B
It will set the carry flag to 0
Clear carry CLRC CLRC
Carry flag<-0
It will set the carry flag to 1
Set carry SETC SETC
Carry flag<-1
Complement It will complement the carry flag
COMC COMC
carry Carry flag<- (Carry flag)’
Enable
EI EI It will enable the interrupt
interrupt
Disable
DI DI It will disable the interrupt
interrupt
73
◉ Shift Instructions: Shifts are operations in which the bits of a word are
moved to the left or right. Shift instructions may specify either logical shifts,
arithmetic shifts, or rotate-type operations. Typical Shift Instructions –
Name Mnemonic
Logical shift right SHR

Logical shift left SHL

Arithmetic shift right SHRA

Arithmetic shift left SHLA

Rotate right ROR

Rotate left ROL

Rotate right through carry RORC

Rotate left through carry ROLC

74
 Micro Processor Organisation

◉ A Microprocessor is an important part of a computer architecture without

which you will not be able to perform anything on your computer.
Basics of Microprocessor –
◉ It performs some basic operations like addition, subtraction, multiplication, division,
and some logical operations using its Arithmetic and Logical Unit (ALU). New
Microprocessors also perform operations on floating-point numbers also.
◉ Data in microprocessors can move from one location to another.
◉ It has a Program Counter (PC) register that stores the address of the next instruction
based on the value of the PC, Microprocessor jumps from one location to another and
takes decisions.

75
◉ Types of Processor: Complex Instruction Set Computer (CISC) –
CISC or Complex Instruction Set Computer is a computer architecture where instructions are
such that a single instruction can execute multiple low-level operations like loading from
memory, storing into memory, or an arithmetic operation, etc. It has multiple addressing nodes
within a single Instruction. CISC makes use of very few registers.
Example:
1. Intel 386 Large Number of Instruction Typically 100 to 250
2. Intel 486 Variable Length instruction format
3. Pentium Instructions that manipulate operands in memory
4. Pentium Pro
5. Pentium II
6. Pentium III
7. Motorola 68000
8. Motorola 68020
9. Motorola 68040 etc.
76
RISC Vs CISC

RISC CISC
RISC focuses on software CISC focuses on hardware
Single clock, reduced instruction only, which means the
Multi-clock complex instructions
instructions are simple compared to CISC

Operates on Register to Register. However, “LOAD” and CISC operates from Memory to Memory: The “LOAD” and
“STORE” are independent instructions “STORE” are incorporated in instructions. Also uses MOVE

RISC has large code sizes, which means it operates low cycles
CISC has small code sizes, high cycles per second
per second
The transistors in a CISC processor are used to store complex
Spends more transistors on memory registers
instructions
Less memory access More memory access

Due to CISC instructions being of variable length, and having

multiple operands, as well as complex addressing modes and
complex instructions this increases complexity. Furthermore,
Implementing pipelining on RISC is easier
CISC as defined above occupies more than a memory word.
Thus taking several cycles to execute operand fetch.
Implementing pipelining on CISC is complicated

77
◉ Reduced Instruction Set Computer (RISC) –
RISC or Reduced Instruction Set Computer is a computer architecture where
instruction is simple and designed to get executed quickly. Instructions get
completed in one clock cycle this is because of the optimization of instructions and
pipelining (a technique that allows for simultaneous execution of parts, or stages,
of instructions more efficiently process instructions). RISC makes use of multiple
registers to avoid large interactions with memory. It has few addressing nodes.
Example:
1. IBM RS6000
2. MC88100
3. DEC Alpha 21064
4. DEC Alpha 21164
5. DEC Alpha 21264

78