Tesla Project Presentation
Tesla Project Presentation
Tesla Project Presentation
PERSONAL DETAILS :
EXPERIENCE :
• Contact: patcha@pdx.edu
• Verification Internship at VINAY PATCHA
• https://www.linkedin.com/in/
Rambus
vinay-patcha/
Simulation of
Last Level Cache
OBJECTIVE
:
ATTRIBUTES
Set Associativity
Block Size
Inclusivity
Write policy
Coherence Protocol
Replacement Policy
Determining Specifications :
Choosing
Write Policies
some
: Write back
specifications
vs Write
involves
through
many factors.
Replacement
Coherence
Policy : LRU
Protocol : VI /
Vs Pseudo
MSI / MESI
LRU
SPECIFICATIONS
Cache size: 16 MB
Address Mapping : 8-way Associative
Block size : 64 Bytes
Write policy : Write Back, Write Allocate
Inclusivity: YES
Coherence protocol: MESI
Replacement Policy: Pseudo - LRU
REASONS
Shared Memory Configuration: The cache
system supports efficient data sharing and
•16 MB LLC & 8-Way Set Associativity: coherence among multiple processors.
Technical Challenges :
Non-Technical Challenges:
I think I can
implement Post Write
Buffers between the
It will have any
LLC and main
effects ? YES
memory. It will avoid
the waiting time
during the flushing.
Thank you