Tesla Project Presentation

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ABOUT ME

EDUCATIONAL DETAILS: SKILLS :

• MS in Electrical and Computer • RTL Design, Verification And


Engineering at Portland State Computer Architecture
University

PERSONAL DETAILS :
EXPERIENCE :
• Contact: patcha@pdx.edu
• Verification Internship at VINAY PATCHA
• https://www.linkedin.com/in/
Rambus
vinay-patcha/
Simulation of
Last Level Cache
OBJECTIVE
:

 SIMULATE A LAST LEVEL CACHE FOR A NEW PROCESSOR THAT CAN BE


USED UP TO THREE OTHER PROCESSOR WHICH IS IN SHARED MEMORY
CONFIGURATION.
CACHE

Cache is a small Generally these Modern processors


memory which is caches are designed use multiple levels
very close to with SRAM cells. of caches to
processor and stores Since SRAM’s are optimize
frequently accessed more speed performance
data to reduce comparatively further.
latency. DRAM.
LLC of
new
processor
Cache Size

ATTRIBUTES
Set Associativity

Block Size

Inclusivity

Write policy

Coherence Protocol

Replacement Policy
Determining Specifications :

Choosing
Write Policies
some
: Write back
specifications
vs Write
involves
through
many factors.

Replacement
Coherence
Policy : LRU
Protocol : VI /
Vs Pseudo
MSI / MESI
LRU
SPECIFICATIONS
 Cache size: 16 MB
 Address Mapping : 8-way Associative
 Block size : 64 Bytes
 Write policy : Write Back, Write Allocate
 Inclusivity: YES
 Coherence protocol: MESI
 Replacement Policy: Pseudo - LRU
REASONS
Shared Memory Configuration: The cache
system supports efficient data sharing and
•16 MB LLC & 8-Way Set Associativity: coherence among multiple processors.

Offers large storage with reduced


memory access and balanced
performance for multi-threaded
environments.
Scalability: The design allows up to
•64-Byte Block Size: Standard size for three other processors to share the
efficient data transfer and compatibility cache levels, facilitating scalable
with modern processors. system architectures.
•MESI Protocol: Ensures cache
coherence and minimizes unnecessary
data transfers in multi-core systems.
•PLRU & Write-Once Policies: Provides High Capacity LLC: The 16 MB LLC
efficient cache replacement and reduces provides ample space for shared data,
write traffic, improving system efficiency reducing memory access bottlenecks in
multi-processor operations.
and power consumption.
DESIGN FLOW
CACHE STRUCTURE

Cache Size = 16MB


Associativity =8

So, no .of index = 2^15


Command and
Address Parsing ::

 The input trace file is in the format :


cmd address
Ex: 2 0x00001343
 cmd represents the operation to be
performed

 Addressed is parsed into tag, index


and byte offset
Pseudo LRU

Why not LRU ?


For n ways, there are n! ordering of
n ways.
⌈log2(n!)⌉ bits needed to encode n!

 Use Pseudo LRU which requires


fewer bits.
 Less die area , Less power
consumption
 Achieves near LRU performance
MESI Protocol:

Protocolslike VI and MSI bottle necks the


performance due to fewer states.

 To maintain cache coherence across all


processors we are using MESI protocol.
 This coherence protocol includes four
states:
 M - Modified
 E - Exclusive
 S - Shared
 I - Invalid
 Initially all the cache lines are invalid state.
Illustration
Index 0 initial data

0 0x00000000 -> Index=0, Tag=0

0 0x00020000 -> Index=0, Tag=1

1 0x00040000 -> Index=0, Tag=2

1 0x00060000 -> Index=0, Tag=3


2 0x000A0000 -> Index=0, Tag=5

0 0x00080001 -> Index=0, Tag=4

0 0x000A0001 -> Index=0, Tag=5

2 0x00020000 -> Index=0, Tag=1

3 0x00060000 -> Index=0,


Tag=3

3 0x00040000 -> Index=0, Tag=2


2 0x000A0000 -> Index=0, Tag=5

3 0x000C0000 -> Index=0, Tag=6

0 0x000C0000 -> Index=0, Tag=6

3 0x00000000 -> Index=0, Tag=0


Challenges

Technical Challenges :

To determine which coherence protocol and replacement policy

Implementing Pseudo LRU functions.

Non-Technical Challenges:

It is a 4 members group project but unfortunately two of my teammates


were dropped this course.
Improvements :

I think I can
implement Post Write
Buffers between the
It will have any
LLC and main
effects ? YES
memory. It will avoid
the waiting time
during the flushing.
Thank you

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