Introduction to

Phase Locked
Loop (PLL)
Presentation Outline

• What is Phase Locked Loop (PLL)

• Basic PLL System
• Problem of Lock Acquisition
• Phase/Frequency Detector (PFD)
• Charge Pump PLL
• Application of PLL
What is Phase Locked Loop (PLL)

• PLL is an Electronic Module (Circuit)

that locks the phase of the output to the
input.
Vi(t) Phase Vo(t)
Locked
Loop
Locked Vs. Unlocked Phase

• Example of locked phase

Vi(t)

Vo(t)

• Example of unlocked phase

Vo(t)

Vi(t)

Phase Error
( ∆φ)
Basic PLL System
•PLL
is a feedback system that detects the phase error
∆φ and then adjusts the phase of the output.
Vi(t) Phase Vo(t)
Locked
Loop
VI
Phase ∆φ Vo
VCO
Detector

• The Phase Detector (PD), detects ∆φ between the

output and the input through feedback system
• Voltage Control Oscillator (VCO) adjusts the phase
difference
Implementation of PD

Phase Detector is an XOR gate

VI
V1 Phase ∆φ Vo
∆φ VCO
Vo Detector

   1 V I 
 0 VI  o
Vo V
Vo(t)

Vi(t)

Phase Error
( ∆φ)
What is VCO ?

• VCO is a circuit module that oscillates at

a controlled frequency ω.
• The Oscillating Frequency is controlled using
Voltage VControl.
ω
– That is why the module is
called ω0
• Voltage Control Oscillator
VControl ω VControl
VCO

  o  KVCOVControl
• Vcontrol must be in the steady state for the VCO
to operate properly
Simple PLL
• Structure
– Phase Detector ( XOR ) that detects the phase error ∆φ
– Low Pass Filter ( to smooth ∆φ )
– Voltage Control Oscillator (VCO)
• Basic Idea
– If VI and Vout are out of phase (unlocked), then the PD
module detects the error and the LPF smoothes the error signal.
The control signal slows down or speeds up the VCO module;
hence, the phase is corrected (locked)
VI
Phase ∆φ
LPF VControl VCO Vout
Detector
Vout ∆φ
Locked Condition

– Locked Condition
d
dt  in out

– that 0
This implies
in out
VI
Phase ∆φ
LPF VControl VCO Vout
Detector
Vout ∆φ
Example: In the UNLOCKED State

VI and Vout has ∆φ at the same

V(t)
i
frequency ω1
• The phase detector must Vo(t)
Phase Error
produce VI
( ∆φ)
• Hence, VCO is dynamically
changing and PD is creating VControl
VControl to adjust for the phase
difference. VControl
ω V1
• ω1
The PLL is in the Locked
ω0
state φ0
V1
VControl
In the UNLOCKED State
• For Simplicity and by using Fourier
Series
•
Let VI
 V cos
V A  VB  1  to 
cos
out
•   to ∆φ,
Due 1PD
t  creates Vcontrol
• VCO will change
out  1 
KVCO VControl
The output voltage B cos 1 t  o 
Vout  Vbecomes
•

(t)
Dynamics of Simple PLL
• PLL is a feedback system
– PD is a gain amplifier
– LPF be first order filter ( as an example)
– VCO is a unit step module
• The transfer function of the feedback system is given
as:
  n2 KPD KVCOLPF
H (s)  out (s)  out (s) H(s)
in s2  2n s
2
  in n  s2  LPF s  KPD KVCO LPF
 
LPF
PD VCO
1
φin KPD s KVCO φout
1
LPF s
Transient Response to PLL
• The unit step response to second order
system
–
– Critically damped
Overdamped ωi
– Underdamped
• Problems with this PLL
– Settling time Vs. ripple of t
Vcontor ωout
– Stability of the system
– Lacks  out in ICs
 outperformance n2
H (s)  (s)  (s)
  in in LPF s 2  2n s 2
n
PD  VCO t
1
φin K φout
KPD s VCO
1 s
LPF
Problem of Lock Acquisition
• When PLL is turned on, the output frequency is far
from the input frequency
• It is possible that the PLL would never lock
• Modern PLL uses FREQUENCY DEDECTOR (FD) in
addition to the PD.

PD
LPF1
Vin
ωin VCO Vout
ω out
FD
LPF2
Phase/Frequency Detector (PFD)
• One Module that detects both frequency and phase
differences
• A
This module B the transition
senses QA QB B
in A or
Initially 0 0 0 0 A QA
PFD
A leads B 0€ 1 0€ 0 0€ 1 0€ 0
XX 0€ 1 1€ 0 0€ 0 B QB
A B QA QB
Initially 0 0 0 0
B leads A 0€ 0 0€ 1 0€ 0 0€ 1
0€ 1 XX 0€ 0 0€ 0
• If A leads B, QA changes its state and QB remains unchanged
• If B leads A, QB changes its state and QA remains
unchanged
A A
B B

QB QB
QA
QA
Application of PLL
• Frequency Multiplications
– The feedback loop has frequency division
– Frequency division is implemented using a counter

VI
PFD ∆φ VControl
LPF VCO Vout

∆φ
Counter
(Frequency
Division)
Clock Skew Reduction
Buffers are used to
distribute the clock
Embed the buffer within the
loop
Application of PLL

• Clock Skew Reduction

– Buffers are used to distribute the clock
– Embed the buffer within the loop
VI
Buffer
PFD ∆φ VControl
LPF VCO Vout
Vout ∆φ

• Jitter Reduction