Data converters and PLDs

Mrs. M.S. Ranade

HOD Computer Engineering Department
 Data converters
• The signals are available in two forms
• Analog signals
• Digital signals
•Sometimes it is necessary to convert analog signal
to digital form or digital signal to analog form
•Electronic circuit used for this conversion is known
as data converter
•The data converters are of two types
• Digital to analog converters (DAC)
• Analog to digital converters (ADC)
• They are available in the IC form
 Digital to analog converter (DAC)
• DAC is an electronic circuit used to convert digital
signal to its analog equivalent
• General block diagram of resistive network DAC
Digital to analog converter (DAC)
Binary weighted resistance DAC
• It consists of resistive network
& a summing amplifier
• Weighted resistors R, 2R, 4R,
8R are used to distinguish each
bit from MSB to LSB
• Weighted resistors are either
connected to reference voltage
or ground depending upon value
of input digital bit
• Digitally controlled electronic
switches are used to switch
between Vref & ground
 Binary weighted resistance DAC
continued
• If input bit is high (logic 1), –Vref will be connected to the
resistor
• If input bit is low (logic 0), the resistor will be grounded
• The output voltage is given by
Vout = -IRf
• The op-amp works as current to voltage converter
Vout = -Rf (V1/R+V2/2R+V3/4R+V4/8R)
• If Rf = R/2, then
Vout = - (V1/2+V2/4+V3/8+V4/16)
= Vref (b3/2+b2/4+b1/8+b0/16)
• Where b3b2b1b0 are digital input bits
 Binary weighted resistance DAC
continued

• Advantages
– Simple construction
– Fast conversion
• Disadvantages
• Expensive
• Requires large range of resistances
• Difficult to maintain accurate ratios over wide range of
resistor values
• Accuracy of DAC depends upon accuracy of resistors
 Binary weighted resistance DAC
continued
• Calculate analog output voltage for 5 bit weighted resistor
DAC for inputs
1. 10110
2. 10001
Assume Vref = 10 V
For 5 bit weighted resistor DAC
Vout = Vref (b4/2+b3/4+b2/8+b1/16+b0/32)
1. Vout = 10(1/2+0+1/8+1/16+0)
= 6.875 V
2. Vout = 10(1/2+0+0+0+1/32)
= 5.3125 V
 R - 2R ladder network DAC

• This circuit also uses digitally controlled electronic

switches
• If a bit is high, Vref will be connected to corresponding
branch
• If a bit is low, corresponding branch will be grounded
 R - 2R ladder network DAC continued
• In this circuit only two values of resistors R & 2R are used
• Op-amp acts as current to voltage converter
• The output voltage is given by
Vout = -IRf
• Output due to b3 = Vref/2R
Output due to b2 = Vref/4R
Output due to b1 = Vref/8R
Output due to b0 = Vref/16R
Vout = - Rf (b3.Vref/2R + b2 .Vref/4R + b1.Vref/8R + b0.Vref/16R )
If Rf = R
Vout = Vref (b3/2 + b2/4 + b1/8 + b0/16 )
R - 2R ladder network DAC continued
• Advantages
– Only two values of resistors R & 2R are required
– No necessity of precision resistors
– Number of input bits can be easily increased

• Disadvantages
• Lower conversion speed than binary weighted resistor
DAC
• Complicated circuit
R - 2R ladder network DAC continued
• A D to A converter has full scale analog output of 10v &
accepts 4 binary bits as input. Find the voltage corresponding
to each analog step
full scale analog output = 10v
full scale output corresponds to b3b2b1b0 = (1111)2
Vout = Vref (b3/2 + b2/4 + b1/8 + b0/16 )
10 = Vref (1/2+1/4+1/8+1/16)
10 = 0.9375 Vref
Vref = 10.666 v
Each analog step corresponds to increment in LSB by 1
Vout = 10.666(0+0+0+1/16) = 0.66619v
R - 2R ladder network DAC continued

V0 0v V8 5.328v
V1 0.666v V9 5.994v
V2 1.333v V10 6.667v
V3 1.998v V11 7.326v
V4 2.664v V12 7.992v
V5 3.33v V13 8.658v
V6 3.996v V14 9.324v
V7 4.662v V15 10v
 DAC specifications
Important characteristics of DAC
•Resolution : it is defined as smallest possible change in analog output
voltage due to unit change in digital input
•High resolution is desirable
•It depends upon number of bits in digital input. Higher the number of
bits, higher is the resolution e.g. 8 bit DAC has 8 bit resolution
•Accuracy : it indicates closeness with which analog output reaches
actual output/its theoretical value
•Accuracy depends upon accuracy of resistors & precision of reference
voltage
•It is specified in terms of %error
•e. g. Maximum output voltage = 10v, accuracy = + 0.2%
maximum error or any output = 0.002 * 10 = 20mv
 DAC specifications continued
• Linearity : there should be linear relationship between digital input &
analog output
• Linearity is defined as difference between desired analog output &
actual output over full range of expected values
• It should be less than +1/2 LSB
• Settling time : when digital input to DAC is changed, analog output
does not change abruptly. Because of presence of switches, stray
capacitance, inductance etc. transients/oscillations may appear in
output voltage
• Settling time is defined as time required for output signal to settle
down to expected value after change in digital input
• Speed : it is rate of conversion of single digital input to its analog
equivalent
• Conversion rate depends on clock, speed of input & settling time of
converter. For rapidly changing inputs conversion speed must be high
 DAC IC 0808

• DAC 0808 is 8 bit digital to analog converter. Analog output

is available in the form of current (I0)
• It is 16 pin IC
• It consists of R- 2R ladder alongwith current switches &
reference current amplifier.
 DAC IC 0808 continued
• A1 to A8 are digital inputs
• If analog output is required in the form of voltage,
external current to voltage converter is needed
• IC requires dual polarity supply voltage +15v
• Reference voltage can be either positive or negative
• Important specifications
– Settling time : 150 nsec
– Power consumption : 33mW at +5v
– Slew rate : 8mA/µsec
– Compatible with : TTL, DTL, CMOS
– Supply voltage range : + 4.5 mV at +5V
 Analog to digital converter (ADC)

• ADC receives analog input & gives n bit digital output

• ADC is an electronic circuit used to convert analog input to its
digital equivalent
• Two types of ADCs we are going to study
• Successive approximation ADC
• Dual slope ADC
Successive approximation ADC

• This ADC is used in medium to high

speed converter
• It is based on approximating input
signal with binary code & then
successively revising this
approximation until best result is
achieved
Successive approximation ADC
continued
• SAR(successive approximation
register) holds current binary value
• SAR receives comparator output,
clock, start conversion signal
• It produces n bit digital output
• It is applied to DAC
• Output of DAC is applied to
comparator
• If Vd<Vi comparator output goes
high
• It is applied to SAR, SAR adjusts
its output accordingly
 Successive approximation ADC
continued
• If Vi<Vd comparator output goes low, then SAR will respond
to this input
• This procedure repeats for all subsequent bits
• Conversion time is n clock cycles for n bit converter
Advantages
• Fixed conversion time
• High speed conversion
Disadvantages
• Complex circuit
• expensive
 Dual slope ADC

• Number of clock pulses recorded by binary counter are related to ratio of

analog voltage & some reference voltage
• Block diagram of dual slope ADC consists of 4 major blocks -
integrator, comparator, binary counter & a switch driven by T flipflop
• When reset pulse is applied feedback capacitor will be discharged,
counter & T flipflop will be reseted
• Output of T flipflop controls the electronic switch
 Dual slope ADC continued
• Electronic switch is initially placed at position 1, which connects
analog input voltage to integrator
• Output of integrator generates a negative ramp, when it crosses
zero volts output of comparator switches to high voltage (at t1),
hence AND gate is enabled
• Clock pulses reach the binary counter, counter starts counting till
it reaches maximum count
• At the next clock pulse (at t2) counter overflows & resets to zero,
hence MSB changes from 1 to 0, it is applied as clock input to T
flipflop, therefore the flipflop toggles, its output changes from 0
to 1 & the switch is thrown to position 2
• Integrator is connected to negative reference voltage VR, hence
integrator output starts increasing towards zero, the counter again
starts counting fresh pulses
 Dual slope ADC continued
• When integrator output crosses zero, output of comparator
goes low. AND gate is disabled. Counter stops counting.
• Number of clock pulses recorded by the counter is
proportional to analog input voltage
Advantages
• Simple & inexpensive
• Better accuracy
• High conversion accuracy
Disadvantages
• Affected by noise
• Cannot be used for high frequency inputs
• Large conversion time
 ADC specifications
Performance criteria of ADC are similar to those for DAC
Following specifications are given by manufacturer of ADC
•Resolution : change in analog input voltage for 1 bit change in
output is called as resolution
•It can be expressed as percentage
•It is given as full scale input voltage divided by total number of
bits % resolution = VFS/2n-1 *100
•Accuracy : accuracy of ADC depends upon circuit components
such as DAC, comparator, reference voltage
•Relative accuracy of ADC is maximum deviation of digital
output from ideal linear characteristic
 ADC specifications continued
• Conversion time : it is the time required for conversion of
analog input to stable digital output
• It depends upon conversion technique used, propagation delay
introduced by circuit components
• It varies with analog voltage. If analog voltage is increased,
conversion time also increases
• Quantization error : digital output is not always accurate
representation of analog input e. g. any value between 1/8 to
2/8 of full scale will be converted to 001
• This approximation process is known as quantization
• Error due to quantization is called as quantization error
• Maximum value of quantization error = + ½ LSB
 ADC specifications continued

• Quantization error should be

as small as possible
• It can be reduced by
increasing number of bits
 ADC IC 0809

• ADC 0809 operates on successive approximation technique

• It is CMOS IC with 8 analog inputs, 8 channel mux, control
logic, resistor voltage divider, group of analog switches &
SAR
 ADC IC 0809 continued
• Out of 8 analog inputs only one will be converted to
equivalent digital signal at a time. Analog input will be
selected using three address lines A,B,C
• ALE input enables address latch, OE pin makes digital output
available on output lines
• 2-1 (MSB) to 2-8 (LSB) are output lines
• Start input begins conversion, end of conversion is indicated
by EOC line
• Important specifications
– Supply voltage Vcc : 5v
– Input voltage range : 0 to 5v
– Power consumption : <15 mW
– Conversion time : 100µS
– Resolution 28
 Memories
• Digital system needs facility for data storage
• A subsystem of digital processing system which can
store the data is known as memory
• Nowadays semiconductor memories of various types
& sizes are used in digital systems
• Major advantages of semiconductor memories are
– Small size
– High speed
– High reliability
– Low cost
– Ease of expansion of memory size
 Memory organization

• Flipflop is used to store 1 bit of information

• Flipflop is basic element of semiconductor memory
• Semiconductor memory is divided into number of sections, each
section is called as memory location
• Each memory location is denoted by a unique number called as
address of that memory location
• Each memory location is used to store a word of required length 8
bit, 16 bit, 32 bit etc. i. e. each memory location consists of
8,16,32 flipflops
 Memory organization continued
• Number of memory locations & number of bits per memory
locations will vary from memory to memory
• Size of memory is specified as M x N, if the memory contains
M memory locations, each of size N bits
• Block diagram of a memory device of size M x N shown
consists of address bus, input data bus, output data bus & a
control bus
• Address bus consists of P number of address input lines to
access M possible locations. Relation between P & M is 2 P = M
e. g. to access 16 memory locations 4 address lines are required.
These lines specify address of memory location where data is to
be stored (write operation) or from where data is to be retrieved
(read operation)
 Memory organization continued
• Input data bus consists of N data input lines. Data which is to
be stored is placed on these lines. This data is N bit long
• Output data bus : data stored at any memory location can be
read & made available on output data bus. It consists of N data
lines
• Input & output data buses are unidirectional ( data flows only
in one direction) / bidirectional ( same data bus can be used for
input data as well as output data)
• Control bus consists of read/write, chip select lines. When
R/W = 1, read operation will be performed & when R/W = 0,
write operation will be carried out
 Classification of memories
Memory devices are classified based on different parameters
•Based on principal of operation
• Sequential access memory
• Random access memory
• Based on physical characteristics
• Erasable memory : information stored can be erased
• Non erasable memory : information stored can not be erased
• Based on retention of information
• Volatile memory : information stored is lost when electric power
is switched off
• Nonvolatile memory : information stored on the chip do not
change even after switching off power supply
• Based on fabrication technology
• Unipolar memory
• Bipolar memory
Sequential & random access memory
• In sequential access method the memory is accessed in a
specific linear sequential manner
• Access time for these memories depends upon location of
data /information
• Examples : magnetic tapes, magnetic disk and optical
memories, shift registers, charge coupled devices
• In random access memory access time is almost same for
every memory location
• It does not depend upon location of information
• Random access memories are further classified as
– Read write memories
– Read only memories
 Random access memory
• Read write memories are referred as RAM
• RAM can read or write data at any address at any time.
• RAMs can be fabricated using unipolar as well as bipolar
technology
• Advantage : it is easy to read/write and flexible to use.
• Disadvantage : it cannot save information for a long
time, in other words, once power is lost, the stored
data will be lost.
• The RAM is further divided into
– SRAM (static random-access memory)
– DRAM (dynamic random-access memory).
 SRAM & DRAM
• SRAM is fabricated using unipolar as well as bipolar
technology
• SRAM cells are basically flipflops
• DRAM saves data by capacitor charging.
• They are formed using unipolar devices(MOSFETS)
• With the development of technology, DRAM has developed
into SDRAM (synchronous DRAM) and DDR SDRAM
( double data rate synchronous dynamic random-access
memory). SDRAM only represents one data on the rising
edge of the clock, while DDR SDRAM can represent one data
on both rising and falling edges. It is used by PC/server
 SRAM

• SRAM cell is used to store & access 1 bit of information.

• It consists of two cross coupled cells T1 & T3, cells T2 & T4 work as
resisters. They act as load to T1 & T3
• X & Y lines are used for addressing the cell
• T5 & T6 control the access to storage cell during read & write
operations
• When X = 1 cells T5 & T6 are selected, hence memory cell will be
connected to data lines
 SRAM continued
• They are used to transfer data for both read & write operations
• To write into the cell, data line is used.
• If it is at logic 1 voltage at node D will be 1. it will make T3 on
& D’ = 0
• If it is at logic 0 voltage at node D = 0, T3 will be off & D’ = 1
• To read the information word line is made high, therefore T5 &
T6 , will conduct & data available at D & D’ will be available
on bitlines/datalines
• SRAM is used for system cache
• Faster than DRAM
• Refreshing not required
 DRAM

• In DRAM data is stored in the form of charge on the capacitor

• DRAM is formed using unipolar devices i. e. MOSFET
• When both control lines are high, MOSFET switch is turned on. It
charges the capacitor
• When row control line is low MOSFET is turned off & the
capacitor retains the charge
• As DRAM cell is made up of only two components, packing
density of DRAM is large as compared to SRAM
• Data is stored as charge on the capacitor, hence DRAM cell needs
periodic refreshing
 Classification of memories continued
• Read Only Memory (ROM): it can only read data in it and
cannot write data to it. Therefore, in this memory data is
already written by the manufacturers, which can’t be modified
again. The common application is the BIOS in the computer.
• The data stored in the ROM can be arbitrarily read. After the
power is turned off, the data in the ROM remains unchanged

• ROM memories can be classified based on development:

• Programmable read only memories (PROM) : these

memories are programmed after manufacturing, by user. They
are programmed using PROM programmer. Once
programmed data in these memories can not be changed
 Classification of memories continued
• Erasable Programmable ROM (EPROM) : these memories
can be erased & programmed again & again. They are
programmed using PROM programmer. Whole memory can
be erased by passing ultraviolet rays through a slit on the chip
for definite amount of time. After erasing chip can be
programmed again
• Electrically Erasable Programmable ROM (EEPROM) :
these memories can be erased & programmed again & again.
They can be erased partially by passing electrical current
through them. These memories are also called as Electrically
Alterable Erasable programmable ROM (EAPROM)
• Content addressable memory (CAM) : this memory is used
in certain very high speed searching application. It is also
known as content associative memory
Classification of memories continued
Programmable Logic Devices (PLDs)
• ICs we have studied so far like mux, adder, counters etc. are
fixed function ICs, as they perform specific functions
Advantages of fixed function ICs for designing logic circuits
• Circuit is easy to test
• Cost of development is low
Disadvantages of fixed function ICs for designing logic circuits
• Need large board space
• Consume large power
• Additional cost for circuit modification
Remedy to this problem is use of application specific integrated
circuit (ASIC). These ICs are designed as per user/application
requirement. But design of ASIC is much complex
 PLDs continued
• Another approach for digital circuit design is use of
programmable logic devices (PLDs)
• Programmable logic device is an IC that is user configurable i. e.
it can be programmed by the user as per requirement
• It is capable of implementing logic functions
• It is LSI chip that contains regular structure
• It allows user to customize it for any specific application
Advantages of PLDs over fixed function ICs
• Reduction in space & power requirement, Low cost
• Compact circuitry, Design security
• High switching speed
• PLDs provide flexibility to the user, they can be reprogrammed in
seconds
 Types of PLDs
• PLD consists of programmable array of logic gates,
interconnections with array inputs & outputs connected to
device pins through fixed elements like buffers & flipflops
• Logic gates may be 2 level AND-OR, NAND-NAND, NOR-
NOR, sometimes AND-OR-EX-OR configuration may be
used
Types of PLDs
• Read Only Memories (ROM)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)
• Complex Programmable Logic Devices (CPLD)
• Field Programmable Gate Array (FPGA)
PLDs are mostly suitable for implementing SOP function
ROM as PLD
• ROM is an array of selectively
unidirectional contacts
• Contacts can be opened or
closed to write required
information into ROM
• 16 bit ROM array uses two 2:4
address decoders, and a data
output i. e. this is 16x1 ROM
• Unidirectional switch in series
with diode at the junction of
every row & column can be
selectively opened or closed
 Programmable Logic Array (PLA)

• PLA shown consists of two level AND-OR circuit on a single chip,

which has M inputs & N outputs
• Number of AND & OR gates and their inputs are fixed for given PLA
chip
• AND gates provide product terms, OR gates sum these product terms
to generate SOP expression
• Internal architecture of PLA consists of input buffers, AND matrix, OR
matrix, invert/noninvert matrix, flipflops/output buffers
Input Buffer (PLA continued )
• Inputs are applied to AND
matrix through input buffers
• Input buffers limit loading of
sources connected at input
• They produce inverted as well
as non inverted inputs
• One buffer is used for each
input line
• AND matrix is used to obtain
product terms
• It has n AND gates with
outputs P0, P1….Pn-1 & 2M
inputs I0, I0’, I1, I1’….IM-1, IM-1’
for each AND gate
AND matrix (PLA continued )
• A fuse link is connected in series
with each diode
• In unprogrammed PLA all links
are intact
• Product term generated by AND
gate is given by
P0 = I0. I0’.I1.I1’…..IM-1.IM-1’
• In unprogrammed device it is zero
• To obtain required product term
unwanted links are opened by
programming e. g. if all links
except links for inputs I0,I2’,I3’
&I6 are opened product term will
be P0 = I0.I2’.I3’.I6
AND matrix (PLA continued )
• Figure shows simplified
presentation of AND matrix &
input buffers
• Interconnections are marked by x
• When AND array is programmed,
desired interconnections are left
with x mark
• Unwanted interconnections are
without x mark
• OR matrix is used to produce sum
of product terms obtained from
AND matrix
• P0,P1,P2 …. are outputs of AND
matrix, which are used as inputs to
OR matrix
OR matrix (PLA continued )
• Outputs of OR matrix are
S0,S1,S2,……SN-1
• Output S0 when all links are
intact is given by
• S0 = P0+P1+P2+…….+Pn-1
• Required sum term can be
obtained by opening unwanted
links by programming
• e. g. S0 = P0 +P1 if fuse links
except for product terms P0 &
P1 are opened
• Figure shows simplified
presentation of OR matrix
 Invert/Non-invert matrix (PLA
continued)

• It is programmable buffer
• It can be set for inverting or non inverting operation
corresponding to active low or active high output respectively
• EX-OR gate or NOT gate can be used for this operation
• In case of EX-OR gate if fuse is intact, output is S, if fuse is
blown output is S’
• Similarly for NOT gate output S or S’ depending upon
whether fuse is intact or open
 Flipflops/output buffers

•Output buffers increase driving capability (sourcing capability) of

PLA
•PLA output is usually TTL compatible
•Output may be totem pole, open collector or tristate
•Figure shows tristate output buffer, when chip enable CE’=0, output
buffers are enabled and outputs will be made available at F 0,F1,…..FN-1
 Flipflops/output buffers continued
• If PLAs are used for state machine applications, output circuit
consists of flipflops and buffers as shown
• Outputs of OR matrix are applied to positive edge triggered
RS flipflops and flipflop outputs are then applied to tristate
buffers to get final outputs F0,F1,…..FN-1
• Programming of PLA is similar to ROM programming. As per
user requirements, manufacturer prepares a mask and desired
data can be stored on PLA
• We can increase capacity of PLA as per user requirement.
• Number of inputs as well as number of outputs of PLAs can be
increased by using different combinations of PLAs
• We can implement different combinational as well as
sequential circuits using PLAs
 PLA IC
• PLAs are commercially available in the form of ICs
IC 82S200
• It is 16 input,48 product terms, 8 output PLA with
tristate outputs
• It is 28 pin DIP
• TTL compatible
• Supply voltage +5v
• Access time 80 nsec
• Power dissipation 600 mw
Design a combinational circuit using
PLA
Implement following functions using PLA
F1 = ∑m(0,3,4,7)
F2 = ∑m(1,2,5,7)
Draw Kmaps for both functions, obtain simplified expressions
then implement using PLA
 Programmable Array Logic (PAL)
• It is programmable array of logic gates on a single chip in AND-OR
configuration
• PAL is used to implement SOP expressions
• It has programmable AND array and fixed OR array i. e. OR array is
non programmable
• Each OR gate gets input from some AND gates, not all
• Input & output circuits of PAL are similar to PLA
• Figure shows PAL configuration for 5 inputs, 8 programmable AND
gates & 4 fixed OR gates
• 5 input buffers produce inverted &non inverted inputs
• 8 programmable AND gates receive 10 inputs, which can be
programmed to generate 8 product terms
• Each of the 4 Fixed OR gates receives inputs from only 2 AND
gates
• Tristate buffers are used on output lines
Programmable Array Logic (PAL)
continued
 Comparison between PLA &PAL

PLA PAL

• Expensive than PAL • Less expensive than PLA

• Complicated to use • Moderately complicated
• AND & OR arrays are • AND array is programmable
programmable OR array is fixed
 Types of PAL devices
• Registered PALs : In these PALs flipflops are available on
output side alongwith output buffers
• These PALs are useful for sequential circuits
• 16 R4, 16R6, 16R8 are examples of registered PALs
• Configurable PALs : In these PALs output capabilities are
enhanced.
• These PALs are equipped with special circuitry called output
macro cells
• A macro cell has circuitry with fuses which can be configured for
various output options
• It increases device flexibility
• It can replace large number of simple PALs
• 22V10 typical configurable PAL with 22inputs,10 outputs & 120
product terms
 Types of PAL devices continued
• Generic array logic devices(GALS) : This is another type of
configurable PAL
• Wide variety of PAL devices can be replaced using GAL
devices
• GAL 16V8 can replace 20 pin PAL devices, GAL 20V8 can
replace 24 pin PAL devices
• Speciality of GAL devices is that OR gate is treated as part of
each macrocell
• It helps to obtain various types of I/O configurations which
can be replaced by GALs
Complex programmable logic devices
(CPLDs)
• PLDs (PLAs &PALs) have limited number of inputs, product
terms & outputs (maximum number of inputs/outputs up to 32)
• If number of inputs/outputs required is more than 32 we can use
CPLD (Complex programmable logic devices)
• Using CPLD we can implement logic circuits equivalent to
10000 logic gates
• Basic architecture of CPLD consists of several blocks
– PAL like blocks
– I/O blocks
– Inter connecting wires
• Input & output lines of various PAL like blocks are connected
to I/O blocks as well as interconnection wires
Complex programmable logic devices
(CPLDs) continued

• Each PAL like block/function block is made of 16 macro cells

• Each macro cell consists of AND-OR combination
• Output of this AND-OR combination is applied to EX-OR gate,
flipflop, mux and tristate buffer
• Every AND-OR combination consists upto 20 AND gates & 1 OR gate
Complex programmable logic devices
(CPLDs) continued

• EX-OR gate works as invert/noninvert buffer

• EX-OR output is stored in D flipflop
• Mux connects either flipflop output or EX-OR output to tristate
buffer depending upon select input
• Tristate buffer acts as switch, its output is connected to I/O pin of IC
• I/O pin acts as output pin if buffer is enabled, else it acts as input pin
 CPLD programming & packaging
• CPLD is programmed in exactly identical way to that of
EEPROM
• They are programmed using In System Programming (ISP) on
the circuit board itself
• CPLDs have large number of pins hence special type of
packages are used
– Plastic leaded chip carrier (PLCC)
– Quad flat pack (QFP)
– Ceramic pin grid array (PGA)
– Ball grid array (BGA)
• Applications of CPLD
• High performance control logic
• Complex finite state machines