Unit -4

LEVELS OF MODELING

Gate Level Modeling: Array of Instances of Primitives, Design of Flip-flops

with Gate Primitives, Delays,.
Dataflow Level Modeling Continuous Assignment Structure, Delays and
Continuous Assignments, Assignment to Vectors.
Behavioral level Modeling: Initial and Always Construct, Assignments with
Delays, Blocking and Non-Blocking Assignments, Procedural Statements,
Assign-De-Assign construct, Parallel Blocks, Force-Release construct.
Functions and Tasks, Design Examples

CO4 : Identify the various levels of modeling of Verilog HDL

 Dataflow Level Modeling
assign c = a && b Example
Continuous
Assignment Structure module andgdf(c,a,b);
output c;
input a,b;
Delays and Continuous wire c;
Assignments assign c = a&&b;
endmodule

Assignment to Vectors
 Dataflow Level Modeling

Continuous
Assignment Structure

Delays and Continuous

Assignments

assign e = a&&b, f = c&&d, g1 = e|f, g = ~g1;

Assignment to Vectors
assign e = a & b;
assign f = c & d;
assign g1 = e ! f;
assign g = ~g1;
 Dataflow Level Modeling
Combining Assignment and Net Declarations
Continuous
Assignment Structure wire c;
assign c = a & b; wire c = a & b;
module aoi2(g,a,b,c,d);
Delays and Continuous output g;
Assignments input a,b,c,d;
wire e,f,g1,g;
assign e = a && b,f = c && d, g1 = e||f, g=~g1;
endmodule
Assignment to Vectors
wire g;
wire e = a && b;
wire f = c && d;
wire g1 = e||f;
assign g = ~g1;
 Dataflow Level Modeling
Continuous Assignments and Strengths
Continuous
Assignment Structure wire (pull1, strong0)g = ~g1;

module aoi4 (g, a, b, c, d);

Delays and Continuous output g;
Assignments
input a, b, c, d;
wire g;
wire e = a &&b;
Assignment to Vectors wire f = c & &d;
wire g1 = e || f;
assign (pull1, strong0)g = ~g1;
endmodule
 Dataflow Level Modeling

Continuous wire c, a, b;
Assignment Structure
assign #2 c = a & b;

Delays and Continuous

Assignments

Assignment to Vectors
 Dataflow Level Modeling

Continuous wire a, b, d;
Assignment Structure wire #2 c;
assign c = a & b;
assign d = a & b;

Delays and Continuous

Assignments

Assignment to Vectors
 Dataflow Level Modeling

Continuous Concatenation of Vectors

Assignment Structure
Example
{ a, b, c }
Delays and Continuous { a(7:4), b(2:0) }
Assignments
Example
module add_8_c(c,cco,a,b,cci);
input[7:0]a,b;
Assignment to Vectors
output[7:0]c;
input cci;
output cco;
assign {cco,c} = (a + b + cci);
endmodule
 Dataflow Level Modeling

Continuous Replicate Vectors

Assignment Structure
Example

Delays and Continuous {2{p}}

Assignments {p, p}
{2{p}, q}
{p, p, q}
Assignment to Vectors
{a, 3 {2{b , c}, d}}
{a, b, c, b, c, d, b, c, b, c, d, b, c, b, c, d }
 Behavioral level Modeling
Initial and Always
Construct
Assignment Left-hand side
type
Assignments with
Delays •Variables (vector/scalar)
Procedural •Occurs within always, initial, task, function
Blocking and Non-
Blocking Assignments •Net (vector/scalar)
Continuous
Assign-De-Assign
construct
•Net or variable (vector/scalar)
Parallel Blocks Procedural •Assign…. Deassign
Continuous •Force……Release

Force-Release
construct

Functions and Tasks

 Behavioral level Modeling
Initial and Always A set of procedural assignments within an initial
Construct construct are executed only once
Assignments with LHS RHS
Delays reg, integer, or real reg, integer, or real
(OR)
Blocking and Non- net
Blocking Assignments
All the procedural assignments are executed sequentially
Assign-De-Assign
construct
reg a,b;
initial
begin
Parallel Blocks a = 1'b0;
b = 1'b0;
Force-Release #2 a = 1'b1;
construct #3 b = 1'b1;
#1 a = 1'b0;
Functions and Tasks #100$stop;
end
 Behavioral level Modeling
Initial and Always Multiple Initial Blocks
Construct module nil1;
initial
Assignments with reg a, b;
Delays begin
a = 1'b0;
Blocking and Non- b = 1'b0;
Blocking Assignments $display ($time,"display: a = %b, b = %b", a, b);
#2 a = 1'b1;
Assign-De-Assign
construct
#3 b = 1'b1;
#1 a = 1'b0;
end
Parallel Blocks initial #100$stop;
initial $monitor ($time, “monitor: a = %b, b = %b", a, b);
Force-Release initial
construct begin
#2 b = 1'b1;
Functions and Tasks end
endmodule
 Behavioral level Modeling
Initial and Always Always
Construct
always block is executed repeatedly and endlessly
Assignments with
Delays
@(negedge clk)
1 to 0
Blocking and Non- 1 to x or z
Blocking Assignments ƒx or z to 0

Assign-De-Assign @(posedge clk)

construct 0 to1
ƒ0 to x or z
Parallel Blocks ƒx or z to 1

@clk
Force-Release
construct
@(prt or clr)

Functions and Tasks

 Behavioral level Modeling
Initial and Always Always
Construct
Example
Assignments with
Delays module counterup(a,clk,N);
input clk;
Blocking and Non- input[3:0]N;
Blocking Assignments output[3:0]a;
reg[3:0]a;
Assign-De-Assign initial a=4'b0000;
construct always@(negedge clk) a=(a==N)?4'b0000:a+1'b1;
endmodule
Parallel Blocks

Force-Release
construct

Functions and Tasks

 Behavioral level Modeling
Initial and Always Always
Construct

Assignments with Example

Delays

Blocking and Non- always@(negedge clk or posedge clr)

Blocking Assignments
a=(clr)?4'h0:((u_d)?((a==N)?4'b0000:a+1'b1):
Assign-De-Assign
((a==4'b0000)?N:a-1'b1));
construct

Parallel Blocks

Force-Release
construct

Functions and Tasks

 Behavioral level Modeling
Initial and Always ASSIGNMENTS WITH DELAYS
Construct
Dataflow Behavioral
Assignments with
Delays Regular Regular(Inter)
Net Intra
Blocking and Non-
Implicit Zero
Blocking Assignments

Assign-De-Assign Example
construct

Parallel Blocks always #3 b = a;

Force-Release
construct

Functions and Tasks

 Behavioral level Modeling
Initial and Always ASSIGNMENTS WITH DELAYS
Construct
Example
Assignments with module del1;
Delays reg a,b;
always #3 b=a;
Blocking and Non- Initial
Blocking Assignments begin
a = 1’b1;
Assign-De-Assign b = 1’b0;
construct #1 a = 1’b0;
#3 a = 1’b1;
Parallel Blocks #1 a = 1’b0;
#2 a = 1’b1;
Force-Release #3 a = 1’b0;
construct end
initial $monitor($time, " a = %d, b = %d", a, b);
initial #20 $finish;
Functions and Tasks
endmodule
 Behavioral level Modeling
Initial and Always ASSIGNMENTS WITH DELAYS
Construct
Example
Assignments with module del2;
Delays reg a,b;
always @(a) #2 b=a;
Blocking and Non- Initial
Blocking Assignments begin
a = 1’b1;
Assign-De-Assign b = 1’b0;
construct #1 a = 1’b0;
#3 a = 1’b1;
Parallel Blocks #1 a = 1’b0;
#2 a = 1’b1;
Force-Release #3 a = 1’b0;
construct end
initial $monitor($time, " a = %d, b = %d", a, b);
initial #20 $finish;
Functions and Tasks
endmodule
 Behavioral level Modeling
Initial and Always  Blocking assignment statements are executed in
Construct the order they are specified in a sequential
block.
 A blocking assignment will not block execution of
Assignments with
Delays statements that follow in a parallel block.
reg x, y, z;
reg [15:0] reg_a, reg_b;
Blocking and Non- integer count;
Blocking Assignments //All behavioral statements must be inside an initial or always
block
Assign-De-Assign initial
construct begin
x = 0; y = 1; z = 1; //Scalar assignments
Parallel Blocks count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
Force-Release #10 reg_b[15:13] = {x, y, z} //Assign result of concatenation
construct to
// part select of a vector
count = count + 1; //Assignment to an integer (increment)
Functions and Tasks
end
 Behavioral level Modeling
Initial and Always
Construct
The simulation times at which the
Assignments with statements are executed are as
Delays follows:
 All statements x = 0 through reg_b
Blocking and Non-
Blocking Assignments = reg_a are executed at time 0
 Statement reg_a[2] = 0 at time = 15
Assign-De-Assign  Statement reg_b[15:13] = {x, y, z}
construct
at time = 25
 Statement count = count + 1 at
Parallel Blocks
time = 25
Force-Release
Since there is a delay of 15 and 10 in
construct the preceding statements, count =
count + 1
Functions and Tasks will be executed at time = 25 units
 Behavioral level Modeling
 Nonblocking assignments allow scheduling
Initial and Always
Construct
of assignments without blocking
execution of the statements that follow in a
Assignments with sequential block.
Delays  A <= operator is used to specify
nonblocking
the statementsassignments.
x = 0 through reg_b =
Blocking and Non-
Blocking Assignments reg_a are executed sequentially at time
0.
Assign-De-Assign Then the three nonblocking
construct
assignments are processed at the same
simulation time.
Parallel Blocks
1. reg_a[2] = 0 is scheduled to
Force-Release
execute after 15 units (i.e., time =
construct 15)
2. reg_b[15:13] = {x, y, z} is
Functions and Tasks scheduled to execute after 10 time
units (i.e.,
 Application of nonblocking assignments
always @(posedge clock)
begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; //The old value of reg1
end
At each positive edge of clock, the following sequence takes place for the nonblocking
assignments.
1. A read operation is performed on each right-hand-side variable, in1, in2, in3, and reg1, at
the positive edge of clock. The right-hand-side expressions are evaluated, and the results
are stored internally in the simulator.
2. The write operations to the left-hand-side variables are scheduled to be executed at the
time specified by the intra-assignment delay in each assignment, that is, schedule "write" to
reg1 after 1 time unit, to reg2 at the next negative edge of clock, and to reg3 after 1 time
unit.
3. The write operations are executed at the scheduled time steps. The order in which the
write operations are executed is not important because the internally stored right-hand-side
expression values are used to assign to the left-hand-side values.
 Behavioral level Modeling
Initial and Always
Construct

Assignments with
Delays

Blocking and Non-

Blocking Assignments

Assign-De-Assign
construct

Parallel Blocks

Force-Release
construct

Functions and Tasks

 Assign-De-Assign construct

 The keywords assign and Deassign are used to

express the first type of procedural continuous
assignment.
 The left-hand side of procedural continuous
assignments can be only be a register or a
concatenation of registers.
 It cannot be a part or bit select of a net or an array
of registers.
 Procedural continuous assignments override the
effect of regular procedural assignments.
 D_FF using assign and deassign statements.
// Negative edge-triggered D-flipflop with asynchronous reset
module edge_dff(q, qbar, d, clk, reset);
output q,qbar; // Inputs and outputs
input d, clk, reset;
reg q, qbar; //declare q and qbar are registers
always @(negedge clk) //assign value of q & qbar at active edge
of clock.
begin
q = d;
qbar = ~d;
end
always @(reset) //Override the regular assignments to q
and qbar
//whenever reset goes high. Use of procedural continuous
assignments.
if(reset)
begin //if reset is high, override regular assignments to q
 D_FF using assign and deassign statements.

// With the new values, using procedural continuous assignment.

assign q = 1'b0;
assign qbar = 1'b1;
end
else
begin //If reset goes low, remove the overriding values by
deassign q; deassigning the registers.
deassign qbar;
//After this the regular assignments q = d and qbar = ~d will be
able to Change the registers on the next negative edge of clock.
end
endmodule
 Parallel Blocks
 Parallel blocks, specified by keywords fork and join,
provide interesting simulation features.
Parallel blocks have the following characteristics:
i. Statements in a parallel block are executed
concurrently.
ii. Ordering of statements is controlled by the
delay or event control assigned to each
statement.
iii. If delay or event control is specified, it is
relative to the time the block was entered.
 All statements in a parallel block start at the time
when the block was entered. Thus, the order in which
the statements are written in the block is not
important.
 Parallel blocks provide a mechanism to execute
 Parallel Blocks
//Parallel blocks with deliberate race condition
reg x, y;
reg [1:0] z, w;
initial
fork //keyword fork can be
viewed as
x = 1’b0; splitting a single flow into
independent flows.
y = 1’b1;
z = {x, y};
w = {y, x};
join
 All statements start at simulation time 0.The order in which the
statements will execute is not known.
 Variables z and w will get values 1 and 2 if x = 1'b0 and y = 1'b1
execute first. Variables z and w will get values 2'bxx and 2'bxx if
x = 1'b0 and y = 1'b1 execute last. Thus, the result of z and w is
 Force-Release construct
 Force and release are used to express the second
form of the procedural continuous assignments.
 They can be used to override assignments on both
registers and nets.
 force and release statements are typically used in
the interactive debugging process, where certain
registers or nets are forced to a value and the effect
on other registers and nets is noted.
 It is recommended that force and release statements
not be used inside design blocks.
 They should appear only in stimulus or as debug
statements.
 Force-Release construct
Force and release on registers
 A force on a register overrides any procedural
assignments or procedural continuous assignments
on the register until the register is released.
 The register variables will continue to store the
forced value after being released, but can then be
changed by a future procedural assignment.
 Force-Release construct
module stimulus;
...
...
//instantiate the d-flipflop
edge_dff dff(Q, Qbar, D, CLK, RESET);
...
...
initial
begin
//these statements force value of 1 on dff.q between time 50 and
//100, regardless of the actual output of the edge_dff.
#50 force dff.q = 1'b1; //force value of q to 1 at time 50.
#50 release dff.q; //release the value of q at time 100.
end
...
...
endmodule
 Force-Release construct
Force and release on nets
 Force on nets overrides any continuous assignments until the net
is released.
 The net will immediately return to its normal driven value when
it is released.
 A net can be forced to an expression or a value.
module top;
...
assign out = a & b & c; //continuous assignment on net out
...
initial
#50 force out = a | b & c;
#50 release out;
end
...
...
endmodule
 Functions and Tasks

 Designers often implement the same functionality in multiple

parts of a behavioral design.
 This repetition can lead to several problems:
• Increased risk of errors
• Difficulty in maintaining code
• Less efficient use of development time

Verilog provides tasks and functions to break up large

behavioral designs into smaller pieces.
Tasks and Functions in Verilog
 Tasks and functions allow the designer to abstract Verilog
code that is used at many places in the design.
 Tasks have input, output, and inout arguments; functions
have input arguments.
 Values can be passed into and out from tasks and functions.
 Functions and Tasks

Functions
Functions are declared with the keywords
function and endfunction. Functions are
used if
all of the following conditions are true for
the procedure:
 There are no delay, timing, or event
control constructs in the procedure.
 The procedure returns a single value.
 There is at least one input argument.
 There are no output or inout arguments.
 There are no nonblocking assignments.
 Functions and Tasks

Tasks:
Tasks are declared with the keywords task and endtask.
Tasks must be used if any one of the following conditions is true
for the procedure:
 There are delay, timing, or event control constructs in the
procedure.
 The procedure has zero or more than one output
arguments.
 The procedure has no input arguments.
 Functions and Tasks

Syntax for Tasks

task_declaration ::=
task [ automatic ] task_identifier ;
{ task_item_declaration }
statement
endtask
| task [ automatic ] task_identifier ( task_port_list ) ;
{ block_item_declaration }
statement
endtask
Functions and Tasks