UNIT 3: Behavioral Descriptions

OBJECTIVES

Understand the concept of sequential statements in VHDL

and how they are different from concurrent statements.

Identify the basic statements and components of behavioral

description such as process, variable assignment
statements, if, case, when, report, loop, exit,
next, always, repeat, forever, and initial.

Review and understand basics of some digital logic systems

such as D flip-flop, JK flip-flop, Binary Counters,
and shift register.

Understand the concept of some basic genetics and

renal system.

HDL Programming Fundamentals

Behavioral is implemented when digital logic structures
are not known or are hard to generate

Examples of such systems are complex arithmetic units,

computer control units, and biological mechanisms

In VHDL, the major behavioral description statement is

process. In Verilog, the major behavioral description
statements are always and initial.
For VHDL, the statements inside the process are sequential.
In Verilog all statements are concurrent.

HDL Programming Fundamentals

3.2 Structure of Behavioral Description

Listing 3.1 Example of HDL Behavioral Description. a) VHDL. B) Verilog.

a) VHDL Description

entity half_add is
port (I1, I2 : in bit; O1, O2 : out bit);
end half_add ;
architecture behave_ex of half_add is
Execution of SA statements
begin
Inside process is
process (I1, I2) Sequential calculation
begin And then assignment
O1 <= I1 xor I2 after 10 ns ; -- statement 1
O2 <= I1 and I2 after 10 ns; -- statement 2

-- The above two statements are signal assignment statements

-- with 10 nano seconds delay.
--Other behavioral (sequential) statements can be added here

end process;
end behave_ex;

HDL Programming Fundamentals

 See Page 67 of the textbook
VHDL Verilog
Event on I1 Event on I1
activates the activates
Process ALWAYS

I1 I1

I2 I2
10 ns 10 ns
O1 O1

O2 O2

1. Calculate O1 (1 xor 0)= 1 1. Calculate: O1 (1 xor 0)= 1, O2 = (1 and 0)= 0

2. Calculate O2 (1 and 0)=0 2. Assign: O1 =1 after 10 ns, O2 = 0 after 10 ns
3. Assign O1 =1 after 10 ns
4. Assign O2 = 0 after 10 ns

HDL Programming Fundamentals

b) Verilog Description
module half_add (I1,I2,O1,O2);
input I1,I2;
output O1,O2;
Execution of statements inside
reg O1,O2; Always is event-concurrent
/* Since O1 and O2 are outputs and they are
written inside “always”, they should be
declared as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1& I2;// statement 2.
/*The above two statements are procedural(inside always) signal assignment
statements with 10 simulation screen units delay*/
/*Other behavioral (sequential) statements can be added here*/
end
endmodule

HDL Programming Fundamentals

 Variable Versus Signal in VHDL

Varb: process(t1)
Signl: process(t1) variable temp1, temp2: bit;
begin begin
st1: S1<= t1; st3: temp1 := t1;
st2: S2 <= not S1; st4: temp2 := not temp1;
end process; st5: S1 <= temp1;
st6: S2 <= temp2;
end process ;
t1
t1
S1
temp1
S2
temp2

S1

S2

HDL Programming Fundamentals

3.4 Sequential Statements
.
3.4.1 IF Statement
IF statement is a sequential statement that appears inside a process
in VHDL or inside always or initial in Verilog. It has several formats;
some of those formats are as follows:
a) VHDL
if ( Boolean Expression)then
statement 1;
statement 2;
statement 3;
.......
else
statement a;
statement b;
statement c;
.......
end if;

See Table 1.15 for a list of relational operators

HDL Programming Fundamentals

b)Verilog
if ( Boolean Expression)
begin
statement 1; /* if only one statement, begin and end
can be omitted */
statement 2;
statement 3;
.......
end
else
begin
statement a; /* if only one statement, begin and end
can be omitted */
statement b;
statement c;
.......
End

See Table 1.15 for a list of relational operators

HDL Programming Fundamentals

else statement can be eliminated; the if statement in this case
simulates a latch:.
a) VHDL

if clk = ‘1’ then ………….Example 3.2

temp := s1;
end if;

Another example
If (clk = ‘1’ and cs =‘1’) then

b) Verilog
if ( clk ==1)
Begin
temp = s1;
end
Another example
If (clk == 1 & cs ==1)
begin

HDL Programming Fundamentals

Example 3.5 Behavioral Description of a 2x1 Multiplexer with Tri-State
Output

Listings 3.2 and 3.3

HDL Programming Fundamentals

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUXBH is Listing 3.3 VHDL elsif
port (A,B,SEL, Gbar: in std_logic; If…..then
Y: out std_logic); elsif….then
end MUXBH; elsif….then
architecture MUX_bh of MUXBH is else
begin end if;
process (SEL,A,B,Gbar)
variable temp: std_logic;
begin
if (Gbar = '0') and (SEL ='1') then
temp :=B;
elsif (Gbar = '0') and (SEL ='0')then
temp := A;
else
temp := 'Z';--Z is high impedance`
end if;
Y <= temp;
end process;
end MUX_bh;

HDL Programming Fundamentals

b) Verilog Description
module MUXBH(A,B,SEL, Gbar,Y);
input A,B,SEL, Gbar;
output Y;
reg Y; /* since Y is an output and appears inside always,Y has to be
declared as reg( register) */
always @ ( SEL,A,B,Gbar) Verilog else if
begin If…..
if (Gbar ==0 & SEL==1) begin……end
begin else if….
Y = B; begin…..end
end
else if (Gbar == 0 & SEL ==0) else if….
Y = A; begin…..end
else
Y = 1'bz; //Y is assigned to high impedance else
end begin….end
endmodule

HDL Programming Fundamentals

3.4.2 Signal and Variable Assignment in VHDL
•Know the difference in execution of signal and variable in VHDL

•To execute Signal we need two phases ( calculate and assign), Variable is
the same as in software languages such as C only one phase to execute.

Example 3.6

HDL Programming Fundamentals

 D Latch using
Variables. The
Wave form is
correct

D Latch using
Signals. The
Wave form is
Wrong

HDL Programming Fundamentals

 3.4.3 Case Statement
case statement is a sequential control statement. It has the following
format:
a)VHDL
case (control-expression) is
when test value or expression1 => statements1;
when test value or expression2 => statements2;
when test value or expression3 => statements3;
when others => statements4;
end case;
b)Verilog
case (control-expression)
test value1: begin statements1; end
test value2: begin statements2; end
test value3: begin statements3; end
default: begin default statements end
endcase

HDL Programming Fundamentals

Example 3.8 Behavioral Description of a Positive Edge Triggered JK
Flip-Flop Using CASE Statement
Listing 3.7
0x
1x x0

0 1

x1

HDL Programming Fundamentals

Example 3.9 3-bit counter with clear
q2 q1 q0

3-bit counter

clr
clk

HDL Programming Fundamentals

module CT_CASE(clk, clr, q);
input clk, clr;
output [2:0] q;
reg [2:0] q;
initial /* The initial procedure is to force the counter to start from initial count q=110
*/
q = 3'b101;
always @(posedge clk)
begin
if (clr ==0)
begin
case (q)
initial as always is
3'd0 : q = 3'd1;
a behavioral
3'd1 : q = 3'd2;
statement
3'd2 : q = 3'd3;
3'd3 : q = 3'd4;
3'd4 : q = 3'd5;
3'd5 : q = 3'd6;
3'd6 : q = 3'd7;
3'd7 : q = 3'd0;
endcase
end
HDL Programming Fundamentals
Example 3.10 Genetics- Listing 3.9
Cells, Chromosomes, DNA, Allele, Dominant allele, Recessive allele,.
Co-Dominant alleles, Gametes, Homozygous in a Gene,
Heterozygous in a Gene, Genotype: Phenotype.

♂
♀ A B O
A AA AB AO
B AB BB BO
O AO BO OO

♂
♀ A B O
A A AB A
B AB B B
O A B O

report , & concatenate (VHDL)

$display, { } concatenate (Verilog)

HDL Programming Fundamentals

3.4.3.1 Verilog Casex and Casez

Example 3.11 Verilog Description of Priority Encoder using Casex

Listing 3.11

HDL Programming Fundamentals

3.4.4 Loop Statement

3.4.4.1 For-Loop

a) VHDL

for i in 0 to 2 loop
if temp(i) = '1' then
result := result + 2**i;
end if;
end loop;
statement1; statement2;....

b) Verilog
for (i=0; i<=2;i=i+1)
begin
if (temp[i] ==1)
begin
result = result + 2**i;
end
end

HDL Programming Fundamentals

3.4.4.2 While Loop

a) VHDL
while (i < x)loop
i := i + 1;
z := i*z;
end loop;
b) Verilog
while(i < x)
begin
i = i +1;
z = i*z;
end

repeat, forever, next, exit pages 93-94

HDL Programming Fundamentals

Example 3.16 Behavioral Description of a 4-bit Positive Edge Triggered Counter
Listing 3.11

Example 3.17 Behavioral Description of a 4-bit Counter with Synchronous Hold

Listing 3.12

HDL Programming Fundamentals

Example 3.18 Calculating the Factorial using Behavioral Description
with While-Loop

Listing 3.13

HDL Programming Fundamentals

Case Study 3.1 Booth Algorithm

HDL Programming Fundamentals

Case Study 3.2 Behavioral Description of a Simplified Renal Antidiuretic
Hormone (ADH) Mechanism

HDL Programming Fundamentals

HDL Programming Fundamentals
HDL Programming Fundamentals
3.6 Summary

Table 3.6 Summary of VHDL statements and their Verilog Counterparts

VHDL Verilog

process always

variable ------

------- reg

if-else-endif if-else-begin end

if-elsif-else-endif if-else if-else-begin end

case-endcase case-begin end

for loop for

while loop while

next, exit -----

------- repeat, forever

MOD %

Signed signed

Srl 1 >> 1

integer integer

HDL Programming Fundamentals