Chapter 3 Gate-Level
Chapter 3 Gate-Level
Gate-Level Minimization
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3-1 Introduction
Gate-level minimization refers to the design task of
finding an optimal gate-level implementation of Boolean
functions describing a digital circuit.
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3-2 The Map Method
The complexity of the digital logic gates
The complexity of the algebraic expression
Logic minimization
Algebraic approaches: lack specific rules
The Karnaugh map
A simple straight forward procedure
A pictorial form of a truth table
Applicable if the # of variables < 7
A diagram made up of squares
Each square represents one minterm
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Review of Boolean Function
Boolean function
Sum of minterms
Sum of products (or product of sum) in the simplest form
A minimum number of terms
A minimum number of literals
The simplified expression may not be unique
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Two-Variable Map
A two-variable map
Four minterms
x' = row 0; x = row 1
y' = column 0; y =
column 1
A truth table in square
diagram
Fig. 3.2(a): xy = m3 Figure 3.1 Two-variable Map
Fig. 3.2(b): x+y =
x'y+xy' +xy =
m1+m2+m3
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Figure 3.2 Representation of functions in the map
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A Three-variable Map
A three-variable map
Eight minterms
The Gray code sequence
Any two adjacent squares in the map differ by only on variable
Primed in one square and unprimed in the other
e.g., m5 and m7 can be simplified
m5+ m7 = xy'z + xyz = xz (y'+y) = xz
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Figure 3.3 Three-variable Map 6
A Three-variable Map
m0 and m2 (m4 and m6) are adjacent
m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'
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Example 3.1
Example 3.1: simplify the Boolean function F(x, y, z) =
(2, 3, 4, 5)
F(x, y, z) = (2, 3, 4, 5) = x'y + xy'
Figure 3.4 Map for Example 3.1, F(x, y, z) = Σ(2, 3, 4, 5) = x'y + xy'
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Example 3.2
Example 3.2: simplify F(x, y, z) = (3, 4, 6, 7)
F(x, y, z) = (3, 4, 6, 7) = yz+ xz'
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Figure 3.3 Three-variable Map 10
Example 3.3
Example 3.3: simplify F(x, y, z) = (0, 2, 4, 5, 6)
F(x, y, z) = (0, 2, 4, 5, 6) = z'+ xy'
Figure 3.6 Map for Example 3-3, F(x, y, z) = Σ(0, 2, 4, 5, 6) = z' +xy'
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Example 3.4
Example 3.4: let F = A'C + A'B + AB'C + BC
a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C)(1, 2, 3, 5, 7) = C + A'B
Figure 3.7 Map for Example 3.4, A'C + A'B + AB'C + BC = C + A'B
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3.3 Four-Variable Map
The map
16 minterms
Combinations of 2, 4, 8, and 16 adjacent squares
F = y'+w'z'+xz'
Figure 3.9 Map for Example 3-5; F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y' + w' z' +xz'
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Example 3.6
Example 3-6: simplify F = ABC + BCD + ABCD +
ABC
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Prime Implicants
Consider F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
The simplified expression may not be unique
F = BD+B'D'+CD+AD = BD+B'D'+CD+AB'
= BD+B'D'+B'C+AD = BD+B'D'+B'C+AB'
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Example 3.7
Example 3.7: simplify F = (0, 2, 4, 6, 9, 13, 21, 23, 25,
29, 31)
F = A'B'E'+BD'E+ACE
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Example 3.7 (cont.)
Another Map for Example 3-7
a) F(A, B, C, D)=(0, 1, 2, 5,
8, 9, 10) =
B'D'+B'C'+A'C'D
b) F' = AB+CD+BD'
» Apply DeMorgan's theorem;
F=(A'+B')(C'+D')(B'+D)
» Or think in terms of maxterms
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Sum-of-Minterm Procedure
Consider the function defined in Table 3.2.
In sum-of-minterm:
F ( x, y , z ) (1,3, 4,6)
In sum-of-maxterm:
F ( x, y , z ) (0, 2,5,7)
Taking the complement of F
F ( x, y , z ) ( x z )( x z )
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Sum-of-Minterm Procedure
Consider the function defined in Table 3.2.
Combine the 1’s:
F ( x, y , z ) xz xz
Combine the 0’s :
F'( x, y , z ) xz x z
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3-6 Don't-Care Conditions
The value of a function is not specified for certain
combinations of variables
BCD; 1010-1111: don't care
The don't-care conditions can be utilized in logic
minimization
Can be implemented as 0 or 1
Example 3.9: simplify F(w, x, y, z) = (1, 3, 7, 11, 15)
which has the don't-care conditions d(w, x, y, z) = (0,
2, 5).
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Example 3.9 (cont.)
F = yz + w'x'; F = yz + w'z
F = (0, 1, 2, 3, 7, 11, 15) ; F = (1, 3, 5, 7, 11, 15)
Either expression is acceptable
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Two-level Implementation
Two-level logic
NAND-NAND = sum of products
Example: F = AB+CD
F = ((AB)' (CD)' )' =AB+CD
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Multilevel NAND Circuits
Boolean function implementation
AND-OR logic → NAND-NAND logic
AND → AND + inverter
OR: inverter + OR = NAND
For every bubble that is not compensated by another small circle
along the same line, insert an inverter.
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3-8 Other Two-level Implementations (
Wired logic
A wire connection between the outputs of two gates
Open-collector TTL NAND gates: wired-AND logic
The NOR output of ECL gates: wired-OR logic
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Figure 3.28 Wired Logic 39
Non-degenerate Forms
16 possible combinations of two-level forms
Eight of them: degenerate forms = a single operation
AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-
NOR, NOR-AND, NOR-NAND.
The eight non-degenerate forms
AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-
AND, OR-NAND, AND-NOR.
AND-OR and NAND-NAND = sum of products.
OR-AND and NOR-NOR = product of sums.
NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?
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AND-OR-Invert Implementation
AND-OR-INVERT (AOI) Implementation
NAND-AND = AND-NOR = AOI
F = (AB+CD+E)'
F' = AB+CD+E (sum of products)
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Tabular Summary and Examples
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November 4, 2024 Figure 3.31 Other Two-level Implementations 45
3-9 Exclusive-OR Function
Exclusive-OR (XOR)
xy = xy'+x'y
Exclusive-NOR (XNOR)
(xy)' = xy + x'y'
Some identities
x0 = x
x1 = x'
xx = 0
xx' = 1
xy' = (xy)'
x'y = (xy)'
Commutative and associative
AB = BA
(AB) C = A (BC) = ABC
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Exclusive-OR Implementations
Implementations
(x'+y')x + (x'+y')y = xy'+x'y = xy
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Four-variable Exclusive-OR
function
Four-variable Exclusive-OR function
ABCD = (AB'+A'B)(CD'+C'D) = (AB'+A'B)(CD+C'D')+
(AB+A'B')(CD'+C'D)
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Parity Generation and Checking
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3.10 Hardware Description Language
(HDL)
Describe the design of digital systems in a textual form
Hardware structure
Function/behavior
Timing
VHDL and Verilog HDL
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A Top-Down Design Flow
Specification
Logic Synthesis
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Module Declaration
Examples of keywords:
module, end-module, input, output, wire, and, or,
and not
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HDL Example 3.1
HDL description for circuit shown in Fig. 3.37
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Gate Displays
Example: timescale directive
‘timescale 1 ns/100ps
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HDL Example 3.2
Gate-level description with propagation delays for circuit
shown in Fig. 3.37
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HDL Example 3.3
Test bench for simulating the circuit with delay
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Simulation output for HDL
Example 3.3
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Boolean Expression
Boolean expression for the circuit of Fig. 3.37
Boolean expression:
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HDL Example 3.4
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User-Defined Primitives
General rules:
Declaration:
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HDL Example 3.5
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HDL Example 3.5 Continued)
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Figure 3.39 Schematic for circuit with_UDP_02467
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