SystemVerilog

Hardware Description Language

(HDL)

Guest lecture
Elena Hammari,
Digital & DFT designer
Nordic Semiconductor ASA 1
 Lecture plan

• Digital design process flow

• Different design views and abstraction levels
• SystemVerilog standard
• SystemVerilog basics:
• Data types
• Number formats
• Negative numbers
• Nets and variables
• Constants
• Arrays
• Assignments
• Operators 2
Classical digital design
flow

3
 Modern digital design HDL description
flow of testbench
HDL description module Mux2to1TestBench
of design logic a = 1’b0;
logic b = 1’b1;
module Mux2to1 logic s,c;
( input logic in0, Mux2to1 MyMux(.in0(a),
input logic in1, .in1(b),.sel(s),.out(c));
input logic sel, initial begin
output logic out); s = 1’b0;
assign out = sel? in1 : in0; assert (c == 1’b0) else
endmodule $error(«Output is not
correct!»);
# 10 ns;
EDA tools* s = 1’b1;
assert (c == 1’b1) else
$error(«Output is not
correct!»);
end
endmodule
EDA
tools
*EDA = Electronic Design Automation, software environments for designing electronic systems 4
 Design abstraction levels

System level Algorithmic level Register transfer level

state
block diagram, machine,
specification data and control flow ALU

Layout
Circuit level Gate level

transistor geometries, nets transistors gates 5

Design views and abstraction levels

HDL

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 Design views and abstraction levels

Behavioral HDL model: Structural HDL model:

module Mux2to1 module Mux2to1(in0, in1,
( input logic in0, sel, out);
input logic in1, EDA tools input in0, in1, sel;
input logic sel, output out;
output logic out); wire tmp1, tmp2, not_sel;

assign out = sel? in1 : and(tmp1, in1, sel);

in0; EDA tools and(tmp2, in0, not_sel);
not(not_sel, sel);
endmodule or(out, tmp1, tmp2);

endmodule

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 SystemVerilog

• Specialized computer language used to describe, verify and implement

electronic circuits, and most commonly, digital logic circuits.
• Described in IEEE 1800 standard, stable release 2017
• Evolved from Verilog, some features from C
• Is used in behavioral and structural design views at multiple abstraction levels
• Parallel programming language:
• Consists of interconnected blocks/processes that run in parallel, like real hardware!
• Only a subset of language constructs are allowed in design description
• Those that can be synthesized into real hardware
• Some constructs are only allowed in verification code
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 SystemVerilog data types

Integers are represented by bits of defined length

• Every bit can have two/four possible states:
0—logic zero or a “false” condition
2-state
1—logic one or a “true” condition data types 4-state
X—an unknown logic value data types
Z—a high-impedance state (“not connected”)

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 SystemVerilog data types
Data types with 2 states (0,1):
Integer data types: TYPE Description Example
bit user-defined size bit [3:0] a_bit;
byte 8 bits, signed byte a, b;
shortint 16 bits, signed shortint c, d;
int 32 bits, signed int i,j;
longint 64 bits, signed longint lword

Data types with 4 states (0,1,X,Z):

TYPE Description Example
logic* user-defined size logic [7:0] a_byte;
integer 32 bits, signed integer i, j, k;
time 64-bit unsigned time now;
* There is also an identical type called reg from older version, but its usage10is discouraged
 SystemVerilog data types

Real data types

• have real values, f.ex. 1.45
TYPE Description Example
shortreal like float in C shortreal f;
real like double in C real g;
realtime identical to real realtime now;

string data type

• A collection of characters
• The length of string is equal to the number of characters
string myName = ’’John Smith’’; string emptyString = ’’ ’’;
• Built-in functions to work on strings: .len(), .substr(int i, int j), .toupper(),
.compare() etc. 11
 SystemVerilog number formats

• Integer number format: [size]’[signed][base][digits]

• size is the number of bits and is optional
• signed: use s or S if the number is signed, default is unsigned
• base: d/D-decimal (default), h/H-hexadecimal, o/O-octal, b/B-binary
• Examples:
758, 'd758, 5'D3, -6, 8'sd6 (decimal integers can be written without size/base)
'h837ff, 16'H9F8E
'o7460, 6'O53
4'b1010, 5'b1101x

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 SystemVerilog number formats

• Real number format: decimal or scientific notation

• In decimal format there must be at least one digit on each side of the decimal point
• Examples: 3847.32 , 0.1 , 1.6e-3 , 2E10 (e or E denotes the exponent
symbol)
• Time format: [integer/real value][time unit]
• Interpreted as a realtime value
• Time units: fs, ps, ns, us, ms, s
• Examples: 40ps, 2.1ns (note: no space!)

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 SystemVerilog negative numbers

Negative integer numbers

• Signed numbers are represented in 2’s complement format
• Notified by letter s → instructs that the number must be interpreted as 2’s complement:
4’shF → 4’sb1111 → -1
• The MSB indicates whether the number is negative or positive:
4’sh7 → 4’sb0111 → 7
• Numbers can also have an explicit sign ’’-’’
• Operator that converts the operand (i.e. the following number) to its 2’s complement
-4’shF → -(4’sb1111)→ 4’sb0001 → 4’sh1
-’sd12 → -(32’b…000_1100)→ 32’b…111_0100 → -12
• If the operand is unsigned, the result is still interpreted as unsigned:
-’d12 → -(32’b…000_1100) → 32’b…111_0100 → 4,294,967,284
• Note that unsized, unbased numbers are signed by default:
-12 signed number in 2’s complement form → 32’b…111_0100 14
 SystemVerilog negative numbers

Negative real numbers

• Represented in floating point format:
• Examples: -1.5, -2.0e-12, -4E20
• Negative numbers have an explicit sign ’’-’’

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 SystemVerilog nets and variables

Two types of data objects:

Nets Variables
• Model connections (wires and busses) • Used to describe logic behavor
in structural descriptions • Store values
• Don’t store values • Can be only continuously driven by
• Can only be driven continuously by one source
one or multiple sources • OR can be written multiple times
• Has conflict resolution with multiple within procedural blocks
drivers • Any data type is allowed
• Only 4-state data types allowed
logic [4:0] nibble_en;
wire [7:0] mybus;
SystemVerilog nets and variables

Variable declaration, initialization and assignment Mux2to1

sel
in0
out
module Mux2to1TestBench variable in1
variable logic a = 1’b0;
logic b = 1’b1; initialization
declaration logic s,c;
Mux2to1 MyMux(.in0(a),
.in1(b),.sel(s),.out(c));
c is driven continuously
initial begin by the out port of MyMux
s = 1’b0;
# 10 ns; s is written several times
s = 1’b1; in the initial procedure
end
endmodule

variable
assignment
 SystemVerilog nets and variables

• A variable is similar to variables in other programming languages

• Can be written by one or more procedural statements
• Can only be driven by a single continuous assignment/port

optional
Variable declaration:
Style 1: Style 2:
[data type] [vector range] [identifier] var [data type] [vector range] [identifier]
logic myVariable; var logic myVariable;
var myVariable; // assumes logic datatype
int i = 1; // initial value 1 var int i = 1;
byte [3:0] myMemoryWord; var byte [3:0] myMemoryWord;
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 SystemVerilog nets and variables

• A net represents a physical connection between gates, blocks

optional
Net declaration:
[net type] [drive/charge strength] [vector range] [data type] [delay] [identifier]
wire myWire; // assumes logic datatype
tri [7:0] myTristateBus; // a tristate bus with 8 bits
wire #5ps w = varA & varB; // continuous assignment as part of
// declaration

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SystemVerilog nets and variables
Built-in net types:
wire tri tri0 supply0
wand triand tri1 supply1
wor trior trireg uwire

Truth table for resolving multiple drivers on wire and tri nets:
wire / tri 0 1 X Z
0 0 X X 0
1 X 1 X 1
X X X X X
Z 0 1 X Z
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SystemVerilog constants

• A constant is a named data object that never changes its value

• Is specified by keywords parameter or localparam
• parameters can be overriden at a higher hierarchy level of the design
• localparams are intended to be used at a single hierarchical level
• Data type and vector range can be specified
• Or defaults to the data type and range of the assigned value

parameter BUS_WIDTH = 32; // integer data type

parameter IDLE = 0, RUN = 1, STOP = 2, READY = 3;
parameter pi = 3.141592; // real data type
localparam DOUBLE_BUSWIDTH = 2*BUS_WIDTH;
localparam logic [31:0] RESET_VALUE = 32'hFFFF_1111

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 SystemVerilog arrays

• Array is a collection of data with the same data type

• Traditionally it was defined for memories and had two set of indices:

logic [7:0] eightBits; // vector of 8 bits

logic [7:0] byteMemory [0:15]; // array of 16 8-bit elements
int Array [0:7][0:31]; // 8-by-32 array of integers
logic [3:0][7:0] qBytes [0:15][1:3];

packed dimensions unpacked dimensions

• declared before array identifier • declared after array identifier
• stored contiguously in memory • arranged in memory non-contiguously
• treated as a single bulk of data • treated element-by-element
• only single bit data types are allowed (bit, logic) • any data type
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 SystemVerilog arrays

• Given an array: packed unpacked

logic [3:0][7:0] qBytes [0:15][1:3];

• A single element is:

qBytes[0][1][3][7]

unpacked packed

• The right-most packed dimension ([7:0]) varies most quickly

• The left-most unpacked dimension ([0:15]) varies most slowly

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 SystemVerilog arrays

Array operations
Reading and writing an array A = B; //unpacked dim must match!
Reading and writing a one-dim. slice A[I:J] = B[K:L];
Reading and writing an element A[I] = B[J];
Equality of array, slice or element if (A == B) …
(Non-equality) if (A[I:J] != B[K:L]) …

Packed array operations

Writing an array from integral value A = 8'b11111111;
Treating as an integer in an expression A+3
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 SystemVerilog arrays

Built-in array functions

$dimensions Total number of dimensions, packed and unpacked
$unpacked_dimensions Number of unpacked dimensions
$left Left bound of a dimension
$right Right bound of a dimension
$size The number of elements in a dimension
$increment 1 if the range decreases, -1 if the range increases
$low The lowest bound of the dimension
$high The highest bound of the dimension

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 SystemVerilog arrays

• Automatic left padding with 0, X or Z:

logic [11:0] a;
a = 'h1; // yields 12'h001
a = 'hz3; // yields 12'hzz3
• Sign extension for signed data types:
logic [11:0] p1 = 4’shA; // p1 = 1111_1111_1010, as sign bit 3 was MSB
logic [11:0] p2 = 5’shA; // p2 = 0000_0000_1010, sign bit was lost!
• Set all bits to the same value: '0, '1, 'X, 'x, 'Z, 'z (note no size specifier!)
a = '1; // same as 12’b111111111111
• Underscores improve readability:
16’b1100_0101_0000_111
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 SystemVerilog arrays

• Concatenation {}
• Forms a single value from several sized values
• Useful for assignment of packed arrays
logic [11:0] vec;
vec = {4’h0, 8’hff} ; // same as 12’h0ff
• For assignment of unpacked arrays ’{} is used
int array[0:3] = ’{1,2,3,4}; // each element assigned separately
int twobyfour[1:4][1:2] = ’{ ’{1,1}, ’{2,2}, ’{3,3}, ’{4,4}};
• Replication {N{…}} or ’{N{…}}
• Used to describe concatenations where the same value is repeated N times:
vec = {4’h0, 2{4’hf}}; // 12’h0ff
array = ’{4{1}};
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 SystemVerilog assignments

• Assigment is the basic mechanism for placing values into nets and
variables
• Similar to statements in software programming languages
• Values can be numeric or an expression containing other nets and variables and
operators
• Two types:
• continuous assignment
• procedural assignment
 SystemVerilog assignments

continuous assignment
• starts with keyword assign (1), or in a net declaration (2)
• the value is assigned with “=” operator
• happens continuously: like a combinational circuit that continuously drives a net
• works on nets or variables
• a single continuous assignment for each variable (3)
(1) (2) (3)
logic a, b, a_or_b; wire enable = powerOn; logic a,b;
assign a_or_b = in_a | in_b; logic enabled; assign a = 1’b1;
assign enabled = 1’b1; assign b = a;
assign a = 1’b0;
Wrong!
SystemVerilog assignments

procedural assignment
• occurs within procedures always, initial, task, function,
• or in a variable declaration
• does not have duration, happens instantaneously
• the variable holds the value until the next assignment
• works only on variables, cannot be used for nets
• can be blocking “=” or non-blocking “<=”

logic a,b,c,d; logic reset = 1;

always_comb begin (2) initial #10 reset = 0;
(1) a = b;
if (c == 1) a = d;
end delay 10 time units
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 SystemVerilog assignments
module myModule;
logic a, b, c, d, e, f;
// Blocking procedural assignments:
initial begin
a = #10 1; // a will be assigned 1 at time 10 Execute in sequential order,
b = #2 0; // b will be assigned 0 at time 12 statements further down are blocked
c = #4 1; // c will be assigned 1 at time 16 by the above statements!
end
// Nonblocking procedural assignments:
initial begin
d <= #10 1; // d will be assigned 1 at time 10
Execute independently of each
e <= #2 0; // e will be assigned 0 at time 2 other, in parallel!
f <= #4 1; // f will be assigned 1 at time 4
end
endmodule
 SystemVerilog operators

• Symbols similar to C
• Some operators target specific data types
• Operators translate to gates when synthesized
• The logic gate realization depends on several factors:
• coding style
• synthesis tool used
• synthesis optimization settings (area, power, timing)
• Not all operators are synthesizable 16-bit adder

logic [15:0] a, b, sum;

logic ci, co;
assign {co, sum} = a + b + ci;
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 SystemVerilog operators

Arithmetic Operators // Given: a = 4’b0011;

// b = 4’b0100;
• Binary operators: (work on two operands) // d = 6; e = 4; f = 2;
+ add a + b // 4’b0111
- subtract b - a // 4’b0001
* multiply a * b // 4’b1100
d / e // 4’b0001 Truncates fraction
/ divide
e ** f // 4’b1111 Not synthesizable
** power
% modulus (the remainder of division)
3 % 2; // 1 Synthesizable!
• Unary operators: (single operand) -7 % 2; //-1 Takes sign of first operand
+ operand is a positive number 7 % -2; // 1 Takes sign of first operand
- operand is a negative number
• If any operand bit has a value ”x”, the result of the expression is all ”x” 33
 SystemVerilog operators

Logical Operators //Given: a = 3 and b = 0, then...

(a && b) // = 0
• Evaluate to a 1-bit value: (b || a) // = 1
• 1 (true), 0 (false) or X (unknown) (!a) // = 0
Binary operators: (work on two operands) (!b) // = 1
&& logical-and // With unknowns: a = 2’b0x; b = 2’b10;
|| logical-or (a && b) // = x
// With expressions:
Unary operator: (single operand) (a == 2) && (b == 3) // = 1 if both
! logical-not // expressions are true

• Operands not equal to zero are equivalent to one

• Can take variables or expressions as operands
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 SystemVerilog operators

Relational Equality Operators

• Evaluate to a 1-bit value:
• 1 (true), 0 (false) or X (unknown) //let a = 4, b = 3,
//x = 4’b1010, y = 4’b1101,
• Operands are compared bit by bit //z = 4’b1xxz, m = 4’b1xxz, n = 4’b1xxx
Binary operators: (work on two operands) a == b // is 0
x != y // is 1
== logical equality x == z // is x
!= logical inequality z === m // is 1
=== logical case equality z === n // is 0
m !== n // is 1
!== logical case inequality
• Zero filling is done if operands are of unequal length
• Logical case inequality allows for checking of x and z values (non-synthesizable!)
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 SystemVerilog operators

Relational Operators
• Return logical 1 if expression is true
• Return logical 0 if expression is false
• Binary operators: (work on two operands)
> greater-than // Let a = 4, b = 3,
< less-than // x = 4’b1010, y = 4’b1101, z = 4’b1xxx
a <= b // 0
>= greater-than-or-equal-to a > b // 1
<= less-than-or-equal-to y >= x // 1
y < z // x

• If any operand bit has a value ”x”, the result of the expression is all ”x”
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 SystemVerilog operators

Relational Operators module less8(

• Expensive and slow operators at gate level input [7:0] a,b,
output z
• 8-bit less-than detector );
• If a is less than (<) b, output is logic one assign z = (a < b) ? 1’b1 : 1’b0;
endmodule

Synthesized gate-level design (schematic):

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 SystemVerilog operators

Bitwise Operators
• Perform bit-by-bit operations
• Mismatched length operands are zero extended
• x and z treated the same
• Binary operators: (work on two operands)
& and, ~& nand
| or, ~| nor
^ xor,
^- , -^ xnor
• Unary operator: (single one-bit operand)
∼ negation 38
 SystemVerilog operators

Bitwise Operators

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 SystemVerilog operators

Bitwise Operators
• Logical operators result in logical 1, 0 or x
• Bitwise operators results in a bit-by-bit value
// let x = 4’b1010, y = 4’b0000
x | y // Bitwise OR, result is 4’b1010
x || y // Logical OR, result is 1

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 SystemVerilog operators

Bitwise Operators
• Give bit-by-bit results:

//8-bit wide AND

module and8(
input [7:0] a,b,
output [7:0] z
);
assign z = a & b;
endmodule

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 SystemVerilog operators

Reduction Operators
•Operate on only one operand
•Perform a bitwise operation on all bits of the operand
•Return a 1-bit result
•Works from right to left, bit by bit
Unary operators: (work on single operand)
& and, ~& nand
//let x = 4’b1010
| or, ~| nor &x //equivalent to 1 & 0 & 1 & 0. Results in 1’b0
^ xor, |x //equivalent to 1 | 0 | 1 | 0. Results in 1’b1
^x //equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1’b0
^- , -^ xnor

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 SystemVerilog operators

Reduction Operators
• Example: generation of parity bit using XOR operator
// 8-bit parity generator
// output is one if odd
// number of ones
module parity8(
input [7:0] d_in,
output parity_out);

assign parity_out = ^d_in;

endmodule

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 SystemVerilog operators

Reduction Operators
•Operate on only one operand
•Perform a bitwise operation on all bits of the operand
•Return a 1-bit result
•Works from right to left, bit by bit
Unary operators: (work on single operand)
& and, ~& nand
// Let x = 4’b1010
| or, ~| nor &x //equivalent to 1 & 0 & 1 & 0. Results in 1’b0
^ xor, |x //equivalent to 1 | 0 | 1 | 0. Results in 1’b1
^x //equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1’b0
^- , -^ xnor
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 SystemVerilog operators

Shift Operators
• Shift operator shifts a vector operand left or right by a specified number of bits, filling
vacant bit positions with zeros.
• Shifts do not wrap around.
• Arithmetic shift uses context to determine the fill bits (sign-filled shift).
Unary operators: (work on single operand)
>> right shift
// Let x = 4’b1100
<< left shift y = x >> 1; // y is 4’b0110
>>> arithmetic right shift y = x << 1; // y is 4’b1000
<<< arithmetic left shift y = x << 2; // y is 4’b0000
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 SystemVerilog operators

Arithmetic Shift Operators

• Arithmetic right shift (>>>)
• shifts right specified number of bits, fill with value of sign bit if
• expression is signed, othewise fill with zero.
• Arithmetic left shift (<<<)
• Shifts left specified number of bits, filling with zero.

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 SystemVerilog operators

Conditional operator ?:
• Operates like the C statement
conditional expression ? true expression : false expression ;
• The conditional expression is first evaluated
• If the result is true, true expression is evaluated
• If the result is false, false expression is evaluated
• If the result is x:
• Both true and false expressions are evaluated,...
• their results compared bit by bit,...
• returns a value of x if bits differ, OR...
• the value of the bits if they are the same.
• This is an ideal way to model a multiplexer or tri-state buffer.
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 References

• IEEE 1800-2017
• http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/
• https://www.quora.com/What-are-the-various-stages-of-a-modern-
digital-design-flow-using-Gajski-and-Kuhn-s-Y-chart

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