VERILOG

SUBMITTED BY

SHAHANA S
M S ALEENA FATHIMA
ARAVIND S G
SAJISHNU M S

[MSc ELECTRONICS (2024-26)]

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 VERILOG

• Verilog is a hardware description language (HDL) used to

model and design digital circuits and systems.

• Introduced in the mid-1980s, it has become one of the

most popular HDLs due to its simplicity, versatility, and
ability to model everything from simple logic gates to
complex processors.

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 RULES & SYNTAX
• Verilog, as a hardware description language, has a unique set of rules and syntax
elements that help describe digital circuits accurately and efficiently.

• The basic lexical conventions used in Verilog HDL are similar to those in the C
programming language.

• Verilog contains a stream of tokens: comments, delimiters, numbers, strings,

identifiers and keywords.

• Verilog HDL is a case-sensitive language. All keywords are in lowercase.

• All lines must end with a semicolon (;).

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Here are the primary rules and syntax structures in Verilog:

Whitespace:

Whitespace can contain the characters for tabs, blanks, and newlines. These
characters are ignored except when they serve to separate other tokens. However, blanks and tabs
are significant in strings.

Comments:

Comments can be inserted in the code for readability and documentation. There are 2
ways to write comments in Verilog,

• A single-line comment starts with // and tells the Verilog compiler to treat everything after this point
to the end of the line as a comment.
• A multiple-line comment starts with /* and ends with */.

a=b&&c; //This is a single-line comment

/*This is a multiple-line
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comment */
Operators:

Operators are special characters used to set conditions or operate on variables. There
are three types of operators: unary, binary, and ternary.

• Unary operators shall appear to the left of their operand.

• Binary operators shall appear between their operands.
• Ternary operators have two separate operators that separate three operands.

a=~b; //~ is a unary operator

a=b&&c; //&& is a binary operator
a=b?c:d; //? : is a ternary operator
a, b, c, and d are operands
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Number Specification:

We can specify constant numbers in binary, decimal, hexadecimal and octal

formats. There are 2 types of number specifications in Verilog: sized and unsized.

(1) Sized numbers:

Sized numbers are represented as <size> `<base format> <number>.

• <size> is only written in decimal and specifies the no. of bits.

• Legal base formats: binary (`b or `B), decimal (`d or `D), hexadecimal (`h or `H), octal (`o or `O).
• <number>: 0 to 9, a to f.
• Uppercase letters are legal for number specification.

4`b111 // This is a 4-bit binary number.

12`habc // This is a 12-bit hexadecimal number.
16`d255 // This is a 16-bit decimal number. 6
(2) Unsized numbers:

• Numbers without a <base format> specification are decimal numbers by default.

• Numbers written without a <size> specification have a default no. of bits depending on the type of
simulator and machine (at least 32 bits).

23456 // This is a 32-bit decimal no. by

default.
`hc3 // This is a 32-bit hexadecimal number.
`o21 // This is a 32-bit octal number.

 Verilog has symbols for unknown ( x ) and high impedance ( z ) values.

 Negative numbers can be specified by putting a minus sign before the size of a constant number.
Having a minus sign between <base format> and <number> is illegal.
 An underscore ( _ ) character is used to improve the readability of numbers and is ignored by
Verilog.
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Strings:

• A string is a sequence of characters that are enclosed by double quotes.

• It must be contained in a single line.
• They are treated as a sequence of 1-byte ASCII values.

“Hello Verilog World” // is a string

“a / b” // is a string

Identifiers and Keywords:

• Keywords are special identifiers reserved to define the language constructs. They are in
lowercase.
• Identifiers are names given to objects so that they can be referenced in the design.
• Identifiers include alphanumeric characters, underscore and dollar signs. They are case-sensitive.
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword; clk is an identifier 8
 MODULES
• A module is a basic building block in Verilog.
• A module is a block of Verilog code that implements certain functionality.

• Modules can be embedded within other modules, and a higher-level module can
communicate with its lower-level modules using their input and output ports.

• A module should be enclosed within a module and endmodule keywords.

• The name of the module should be given right after the module keyword, and an
optional list of ports may be declared as well.

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COMPONENTS OF A VERILOG MODULE

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 PORTS
• Port is an essential component of the Verilog module.

• Ports are used to communicate for a module with the external world through
input and output.

• Every port in the port list must be declared as input, output or input.

• Ports, also referred to as pins or terminals, are used when wiring the module to
other modules.

• If the module does not exchange any signals with the environment, there are no
ports in the list.

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 TYPES OF PORTS

PORT DESCRIPTION

The design module can only receive values from outside using its
Input input ports.

The design module can only send values to the outside using
Output its output ports.

The design module can either send or receive values using

Inout its inout ports.

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 VARIABLES
In Verilog, variables are used to store and manipulate data within hardware descriptions.
Here’s a breakdown of the variables used in Verilog:

Wire
Reg
Integer
Parameter
Real
Time
Logic
Genvar
Each type of variable serves different purposes in Verilog, whether modelling combinational
logic, storing values across clock cycles, or defining constants. 13
 Wire:

Represents physical connections between hardware components, often used to model

combinational logic.

 Reg:

Used inside procedural blocks like always and initial. It holds values between clock
cycles and is commonly used in sequential logic.

 Integer:

Store integers and is often used for loop counters or procedural assignments. It is 32-
bit wide by default.
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 Parameter:

Used to define constants that can be used throughout a module, often for setting
fixed values like bus widths or time delays.

 Real:

Stores real numbers. Rarely used in synthesizable code, typically for testbenches.

 Time:

Often used to store simulation time values in testbenches. It is 64-bit wide by default.

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 Logic:

A multi-driven signal used for both combinational and sequential logic. It replaces
wire and reg in many cases in SystemVerilog.

 Genvar:

Used in generate loops to create parameterized hardware structures.

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 DATA TYPES
The primary intent of data types in the Verilog language is to represent the data storage
elements like bits in flip-flops and transmission elements like wires that connect
between logic gates and sequential structures.

The following are the data types used in Verilog:

 Value set
 Nets
 Registers
 Vectors
 Integer, real and time
 Arrays
 Memories
 Parameters
 Strings
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 Value Set:

The Verilog HDL value set consists of four basic values:

VALUE DESCRIPTION

0 Logic zero or false

10 Logic one or true

x Unknown value

z High impedance

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 Nets:

• Nets are used to connect between hardware entities like logic gates and hence do not
store any value.

• The net variables represent the physical connection between structural entities such
as logic gates.

• These variables do not store values except trireg. These variables have the value of
their drivers, which changes continuously by the driving circuit.

• Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0,
supply1, and trireg.

• A net data type must be used when a signal is:

o The output of some devices drives it.
o It is declared as an input or in-out port.
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o On the left-hand side of a continuous assignment.
1. Wire
A wire represents a physical wire in a circuit and is used to connect gates or
modules. The value of a wire can be read, but not assigned to, in a function or block. A wire
does not store its value but must be driven by a continuous assignment statement or by
connecting it to the output of a gate or module.

2. Wand (wired-AND)
The value of a wand depends on the logical AND of all the drivers connected to it.

3. Wor (wired-OR)
The value of wor depends on the logical OR of all the drivers connected to it.

4. Tri (three-state)
All drivers connected to a tri must be z, except one that determines the tri's value.

5. Supply0 and Supply1

Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power).
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 Registers:

• Registers represent data storage elements

• It does not need a driver or a clock.
• They retain value until another is placed onto them.
• Register data types are commonly declared by the keyword reg.
• The default value for a reg data type is x.

 Vectors:

• Net or reg data types can be declared as vectors(multiple bit widths).

• If bit with is not specified, the default is scalar (1-bit)

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 Integer, Real and Time Register Data Types:

1. Integer:
• It is a general-purpose register data type used for manipulating quantities.
• Integers are declared by the keyword integer.
• Default width – 32 bits

2. Real:
• Real number constants and real register data types are declared with the keyword
real.
• When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.
• Default value – 0

3. Time:
• Time for storing simulation times in test benches.
• It can be used in conjunction with the $time system task to hold simulation time.
• Default width – 64 bits
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 Arrays:
• Arrays are multiple elements that are 1-bit or n-bis wide.
• Arrays are allowed in Verilog for reg, integer, time and vector register data types.
• Arrays are not allowed for real variables.
• Arrays are accessed by <array_name>[<subscript>].

 Memories:
• Memories are modelled in Verilog as an array of registers.
• Each element of the array is known as a word.
• Each word can be one or more bits.

 Parameters:
• Verilog allows constants to be defined by the keyword parameters.
• Module behavior can be altered by simply changing the value of a parameter. 23
 Strings:

• Strings can be stored in reg.

• Each character in the string takes up 8 bits(1 byte).

• If the width of the register is greater than the size of the string, Verilog fills
bits to the left of the string with zeroes.

• If the width of the register is smaller than the size of the string, Verilog
truncates the leftmost bits of the string.

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 OPERATORS
Operators act on the operands to produce desired results. Each operator is denoted by
a symbol.

Verilog provides various types of operators as follows:

 Arithmetic
 Logical
 Relational
 Bitwise
 Equality
 Reduction
 Shift
 Concatenation
 Conditional
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 ASSIGNMENT
Placing values onto variables and nets is called assignments.

There are three necessary forms:

1. Procedural
2. Continuous
3. Procedural continuous

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 LEGAL LHS VALUES
An assignment has two parts, the right-hand side (RHS) and left-hand side (LHS)
with an equal symbol (=) or a less-than-equal symbol (<=) in between.

ASSIGNMENT TYPE LEFT-HAND SIDE

o Variables (vector or scalar)

o Bit-select or part-select of an integer, vector reg, or time variable.
Procedural o Memory word.
o Concatenation of any of the above.

o Net (vector or scalar)

Continuous o Bit-select or part-select of a vector net.
o Concatenation of bit-selects and part-selects.

o Variable or net (scalar/vector)

Procedural Continuous o Part-select or bit-select of a vector net.
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 Procedural Assignments:
 Procedural assignments occur within procedures such as initial, always, task,
and functions are used to place values onto variables. The variable will hold the
value until the next assignment to the same variable.

 The value will be placed onto the variable when the simulation executes this
statement during simulation time. This can be modified and controlled the way we
want by using control flow statements such as if-else-if, looping, and case
statement mechanisms.

Variable Declaration Assignment:

o An initial value can be placed onto a variable at the time of its declaration.

o The assignment does not have a duration and holds the value until the next
assignment to the same variable happens.

o The variable declaration assignments to an array are not allowed. 30

 Continuous Assignments:

 This is used to assign values to scalar and vector nets. And it happens whenever there is
a change in the RHS.

 It provides a way to model combinational logic without specifying an interconnection of

gates and makes it easier to drive the net with logical expressions.

Net Declaration Assignment:

o This allows us to place a continuous assignment on the same statement that declares
the net.

o Only one declaration assignment is possible because a net can be declared only once.

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 Procedural Continuous Assignments:
These are procedural statements that allow expressions to be continuously assigned to variables or nets.
And these are the two types.

1. Assign deassign:
• It will override all procedural assignments to a variable and deactivate it using the same signal
with deassign.

• The value of the variable will remain the same until the variable gets a new value through a procedural or
procedural continuous assignment.

• The LHS of an assign statement cannot be a part-select, bit-select, or an array reference, but it can be a
variable or a combination of the variables.

2. Force release:
• These are similar to the assign deassign statements but can also be applied to nets and variables.

• The LHS can be a bit-select of a net, part-select of a net, variable, or a net but cannot be the reference
to an array and bit or part-select of a variable.

• The force statement will override all other assignments made to the variable until it is released using
the release keyword. 32
 VERILOG TESTBENCH
 The testbench is written to check the functional correctness based on
design behavior.

 The connections between the design and testbench are established

using a port interface.

 A testbench generates and drives a stimulus to the design to check its

behavior.

 Since the behavior of the design has to be tested, the design module is
known to be “Design Under Test” (DUT).

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 MEMORY
 Memories are digital storage elements that help store data
and information in digital circuits.

 RAMS and ROMS are good examples of such memory

elements.

 Storage elements can be modelled using one-dimensional

arrays of types [reg] and are called memory.

 Each element in the memory may represent a word and is

referenced using a single array index.
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 In digital simulation, one often needs to model register files,
RAMS and ROMS. Memories are modelled in Verilog simply as a
one-dimensional array of registers.

 Each element of the array is known as an element or word and is

addressed by a single array index.

 Each word can be one or more bits. It is important to differentiate

between n1 bit registers and one n bit registers.

 A particular word in memory is obtained by using the address as

a memory array subscript.
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 FILE – READ & WRITE
 File reading and writing is a very useful thing to know in Verilog.

The file input-output functions format is based on the C standard

input–output routines, such as fopen, fgetc, fprintf, and fscanf.

The Verilog language has a set of system functions to write files

(&fdisplay, &fwrite, etc) but only reads files with a single, fixed
format (&readmem).
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 The possibility to read test input values from files, and
write output values for later verification makes test
bench codes easy to write and understand.

 There are a few ways to read or write files in Verilog.

 The method described will help you to read the

contents of a file line by line, instead of reading
everything together. This is helpful when the size of the
file is too big.

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 REFERENCE
 Verilog HDL: A Guide to Digital Design and Synthesis - SAMIR PALNITKAR

 https://www.javatpoint.com/verilog

 https://www.chipverify.com/tutorials/verilog

 https://vlsiverify.com/verilog/writing-a-testbench-in-verilog/

 https://www.slideshare.net/slideshow/verilog-operatorspptx/251696451

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