MEMORY AND PROGRAMMABLE

LOGIC

Zahraa abdulameer

Supervised by
Dr. Alaa.H.Ali
2023/10/23
 INTRODUCTION

• There are two types of memories that are used in digital

systems:
Random access memory (RAM): performed both the write
and read operations.
Read only memory (ROM): performed only the read
operation.
• The RAM is programmable logic device (PLD).
other units are the programmable logic array(PLA) ,
programmable array logic(PAL) , and the field programmable
gate array(FBGA).
 RANDOM-ACCESS MEMORY

• A memory units stores binary information in groups

of bits called words.
1 byte = 8 bits
1 word = 2 bytes or more
• The communication between memory and its
environment is achieved through data input and
output lines, address selection lines, and control
lines that specify the direction of transfer.
RANDOM-ACCESS MEMORY

Block diagram of a
 RANDOM-ACCESS MEMORY

• Each word in memory is

assigned an identification
number, called an address,
starting from 0 up to - 1,
where k is the number of
address lines.
• the number of words (or bytes)
in memory with one of the
letters:

G
 WRITE AND READ OPERATIONS

Write operation: transferring a new word to be

stored into memory are as follows:
1.Apply the binary address of the desired word to the
address lines.
2.Apply the data bits that must be stored in memory to
the data input lines.
3.Activate the write
read operation: input. a stored word out of memory
transferring
1. Apply the binary address of the desired word to the address
lines.
2. Activate the read input.
 WRITE AND READ OPERATIONS

• Commercial memory components available in

integrated‐circuit chips sometimes provide the two
control inputs for reading and writing in a
somewhat different configuration
 TIMING WAVEFORMS

• The memory does not employ an internal clock. Instead, its read
and write operations .The CPU must provide the memory control
signals in such a way as to synchronize its internal clocked
operations with the read and write operations of memory.
• access time of memory is the time required to select a word
and read it. The cycle time of memory is the time required
to complete a write operation
• The memory enable and the read/write signals must be
activated after the signals in the address lines are stable in
order to avoid destroying data in other memory words.
 MEMORY DECODING

Internal Construction

1 3
bit input ,1outpu
1 0
t

Memory
 0
4 word =
2 address
lines1 0
0
1 0

0 = all output 0
is 0
1= one of 4
words is
selected
0

Diagram of a 4 * 4 RAM
 COINCIDENT DECODING

LSB

AND=32+32=64
instead of
1024 AND if we use
one dimension

word

MS
B

Two‐dimensional decoding
structure for a 1K‐word
memory
 A D D R E S S M U LT I P L E X I N G

Because of their large

101 capacity, the address
decoding of DRAMs is
colum
arranged in a
n
two‐dimensional array
addres
the address is applied in
s
two parts at different
strobe
times, with the row
1 01 address first and
the column address
row
second
addre
registers are used to
ss
store the addresses of the
strobe
row and column

Address multiplexing for a 64K DRAM

 ERROR DETECTION AND
CORRECTION

• The dynamic physical interaction of the electrical signals

affecting the data path of a memory unit may cause occasional
errors in storing and retrieving the binary information.
• The most common error detection scheme is the parity bit. The
parity of the word is checked after reading it from memory. The
data word is accepted if the parity of the bits read out is correct.
If the parity checked results in an inversion, an error is detected,
but it cannot be corrected.
 HAMMING CODE

• One of the most common error‐correcting codes used in RAMs.

• k parity bits are added to an n ‐bit data word , The bit positions are
numbered in sequence from 1 to n + k.
Bit 1 2 3 4 5 6 7 8 9 10 11 12
position
n+ k p1 p2 1 p4 1 0 0 p8 0 1 0 0
• exclusive‐OR operation performs the odd function: It is equal to 1 for
an odd number of 1’s in the variables and to 0 for an even number of
1’s.
Bit 1 2 3 4 5 6 7 8 9 10 11 12 Result
position
P1 XOR of : p1 p2 1 p4 1 0 0 p8 0 1 0 0 0
P2 XOR of : p1 p2 1 p4 1 0 0 p8 0 1 0 0 0
P4 XOR of : p1 p2 1 p4 1 0 0 p8 0 1 0 0 1
P8 XOR of : p1 p2 1 p4 1 0 0 p8 0 1 0 0 1
• When the 12 bits are read from memory, they are checked again for
errors. The parity is checked over the same combination of bits,
including the parity bit. The 4 check bits are evaluated as follows:
• C1 = XOR of bits (1, 3, 5, 7, 9, 11)
• C2 = XOR of bits (2, 3, 6, 7, 10, 11)
• C4 = XOR of bits (4, 5, 6, 7, 12)
• C8 = XOR of bits (8, 9, 10, 11, 12)
• C = C8C4C2C1 = 0000, no error. , if C≠0, then the 4‐bit binary number
formed by the check bits gives the position of the erroneous bit.
Bit 1 2 3 4 5 6 7 8 9 10 11 12 C8 C4 C2 C1
position
No error 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0
Error in bit 1 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1
1
Error in bit 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 1
5
 READ‐ ONLY MEMORY

• A ROM is essentially a memory device, consisting of k inputs and n

outputs.
• The number of words in a ROM is determined from the fact that k
address input lines are needed to specify words.
• A ROM does not have data inputs, because it does not have a write
operation.

Rom block
diagram
 Open=
A fuse that can * 0
be blown by Close
* =1
applying a high
*
voltage pulse blowin
g

* A
crosspoint

Internal logic of a 32 *8
 COMBINATIONAL CIRCUIT
IMPLEMENTATION
• The ROM is essentially a device that includes both the decoder
and the OR gates, so we were able to generate any desired
combinational circuit.
• A ROM has two operations :
1. A fixed memory unit.
2. A combinational circuit unit.
• The sum of minterms is
A7(I4, I3, I2, I1, I0) =∑ (0, 2, 3, …, 29)
• All that the designer has to do is specify the particular ROM by its
IC number and provide the applicable truth table. No internal logic
diagram is needed to accompany the truth table.
 2
𝐼𝑁

Programming the ROM according

 C O M B I N AT I O N A L P R O G RA M M A B L E LO G I C D E V I C E
PLDS

programmable gate array implement Boolean functions

 PROGRAMMABLE LOGIC ARRAY

3
IN
Product
term

=
True and
1=
compleme ′ ′ ′
nt 𝐹 1= 𝐴 𝐵 + 𝐴𝐶 + 𝐴 𝐵 𝐶

′
𝐹 2=( 𝐴𝐶 + 𝐵𝐶 )
Sum of
Products 2 OUT
• The PLA programming table consists of three sections:
1. The first section lists the product terms numerically.
2. The second section specifies the required paths between inputs
and AND gates.
3. The third section specifies the paths between the AND and OR
gates. For each output variable, we may have a T (for true) or C
(for complement) for programming the XOR gate.
• Connection from IN=1
Connection from complement=0
Blown fuse=dash(It is assumed that an open terminal in the
input of an AND gate behaves like a 1 ).
1 2 3

Path Path
between IN between
and AND AND and OR
 EXAMPLE

• Implement two Boolean functions with a PLA:

•
 AND=10 1N
PAL
F1
4 IN 4 OUT
buffer–
I1 inverter
gate

F2

I2

F3

I3 Three wide
Four
sections
F4

I4
• As an example of using a PAL in the design of a combinational circuit,
consider the following Boolean functions, given in sum‐of‐minterms form:
• w(A, B, C, D) = ∑(2, 12, 13) y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
• x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15) z(A, B, C, D) = ∑(1, 2, 8, 12, 13)
 SEQUENTIAL PROGRAMMABLE
DEVICES
• Sequential programmable devices include both gates and flip‐flops.
• we will describe three major types :
1. Sequential (or simple) programmable logic device (SPLD)
2. Complex programmable logic device (CPLD)
3. Field‐programmable gate array (FPGA)

SPL
D
• Each section of an SPLD is called a macrocell, which is a circuit that
contains a sum‐of‐products combinational logic function and an
optional flip‐flop.
• A typical SPLD has from 8 to 10 macrocells in one IC.

Three
state
buffer

Basic macrocell logic

 CPLD
• The switch matrix receives inputs from the I/O block and directs them to the individual
macrocells. Similarly, selected outputs from macrocells are sent to the outputs as
needed.
• Each PLD typically contains from 8 to 16 macrocells.

IC bins

General CPLD
 A FIELD‐PROGRAMMABLE GATE ARRAY (FPGA)

• A typical FPGA logic block consists of lookup tables, multiplexers,

gates, and flip‐flops. A lookup table is a truth table stored in an SRAM
and provides the combinational circuit functions for the logic block.
• The design with PLD, CPLD, or FPGA requires computer‐aided design
(CAD) tools to facilitate the synthesis procedure. Synthesis tools are
available that allocate, configure, and connect logic blocks to match
a high‐level design description written in HDL, such as ABEL,VHDL,
and Verilog. As an example of CMOS FPGA technology, we will discuss
the Xilinx FPGA.
• Basic Xilinx Architecture
• Spartan-3E offers 1.6M
gates plus block RAM
• CLB [programmable
lookup table, multiplexers,
registers, and paths for
control signals]

Basic architecture of Xilinx

Spartan and predecessor
THANKS FOR LISTENING