Unit 3 Chapter1 Computer Arithmetic
Unit 3 Chapter1 Computer Arithmetic
Chapter 1
Computer
Arithmetic
Sign-magnitude
XOR
gates
Algorithm:
Like as: A= -2 ,
B=5
2’s complement addition and
subtraction:
Multiplication
algorithms:
A binary
example:
Partial
product
Hardware
implementation #of bit in multiplier
multiplier
Partial
product
Algorithm
:
B=11011 Q=00111
4 Q4=1,A=0,Qs
=1
EA=A+B=1011
EAQ= 0
1011
0111
Shr EAQ= 0
0101
1011
3 Q3=1
EA = 1 0000
EAQ 1 0000 1011
Shr EAQ 0 1000 0101
2 Q2=1
EA= 1 0011
EAQ 1 0011 01 01
shr EAQ 0 1001 101 0
Booth multiplication
algorithm
A= 00011 B= 00111 => A*B= A*(7)=A* (8-1)=A*8-
A*1
If A-B>= 0 then
DVF1
Other
methods:
• Comparison Method : Here A and B compared
prior to the subtraction operation. Then if
A>=B, B I subtracted from A. If A<B nothing is
done.
• Non-restoring: in the restoring method
when A<B 2(A-B+B)-B=2A-B,
A<B 2(A-B)+B=2A-B
Floating point
operations
• The standard format:
IEEE 754 single
precision
The multiplication of the mantissas is done as in the fixed-point case with the product
residing in A and Q . Overflow cannot occur during multiplication, so there is no need
to check for it. The product may have an underflow, so the most significant bit in A is
checked. If it is a 1, the product is already normalized. If it is a 0, the mantissa in AQ is
shifted left and the exponent decremented. Note that only one normalization shift is
necessary. The multiplier and multiplicand were originally normalized and contained
fractions. The smallest normalized operand is 0.1, so the smallest possible product is
0.01. Therefore, only one leading zero may occur.
Although the low-order half of the mantissa is in Q, we do not use it for the floating-
point product. Only the value in the AC is taken as the product.
Division
: