MPMC

Term:2015-2016
III Year B.Tech I Sem

Unit-I PPT Slides

COURSE OBJECTIVE: The objective of this course is to impart a solid
understanding of the Role of Computer systems, Microprocessors and
Microcontrollers.

 COURSE OUTCOMES:
Acquires the basic knowledge on Computer system and their memory system.
 Acquires the basic knowledge on Microprossesors-8085, 8086.
 Understand programming Concept of 8086.
 Understands the interfacing of various advanced devices with 8086-
Microprossesor.
 Acquires an basic knowledge Serial communication and their standards.
 Understands the basic microcontrollers---8051 and their programming.
 Acquires an basic knowledge of RISC Controller.
 COMPUTER
ORGANIZATION
UNITWISE COURSE OBJECTIVE

UNIT-I
To study different Types of Computer.
To understand the Functional Units of Computer.
To understand the Basic Operational Concepts of Computer System.
To know about Data Representations in different forms.
To understand Concepts of Various Memories.

UNIT-II
To discuss the Architecture of 8086
To discuss the pin description of 8086.
To discuss the various addressing modes and instruction set of 8086
To understand ALP programming Concept of 8086
To know about modes of 8086 and Timing Diagrams
To understand Macros and Procedures.
UNIT-III

 To understand the concept of 8255-PPI and to interface it with 8086.

 To understand how to interface Displays,keyboards,Stepper Motor with 8086.
 To understand the concept of serial communication schemes RS-232, IEEE-488.
 To understand 8251 USART architectures and interfacing with 8086.
 To discuss about the Prototyping and trouble shooting.
 To understand the concept of memory interface.
 To know the concept of DMA transfer and its mode of operation.
 To understand the concept of interrupt & understand the concept of 8259 PIC
architecture and its interface with 8086.
 To know BIOS/DOS instructions
UNIT-IV

 To understand the basic concept of 8051 microcontroller---its architecture.

 To discuss about the memory organization of 8051 microcontroller.
 To discuss about various addressing modes and instruction set of 8051.
 To discuss about recent Microcontrollers such as AVR.
 To discuss about instruction execution timers serial communication.
 To understand the concept of interrupt

UNIT-V

 To study the operation of timers, counters & serial communication of 8051 MC.
 To understand the programming concept of external interrupt in 8051 MC.
 To understand how a timer are programmed in 8051 microcontroller
UNIT-I COURSE OBJECTIVE

To study different Types of Computer.

To understand the Functional Units of Computer.
To understand the Basic Operational Concepts of
Computer System.
To know about Data Representations in different
forms.
To understand Concepts of Various Memories.
 UNIT 1 SYLLABUS
1.1 Computer Types
1.2 Functional Units
1.3 Basic Operational Concepts
1.4 Data Representation, Fixed Point
Representation and Floating Point
Representation
1.5 Memory System:
1.5 .1 Concepts of Semiconductor RAM
Memories
1.5.2 ROM
1.5 .3 Cache Memories
1.5 .4 Virtual Memories
 Unit 1. University Questions
1. What are the different types of Mapping
Techniques used in the usage of Cache Memory?
Explain.
2. Explain the following with applications for each:
(a) ROM
(b) PROM
(c) EPROM
(d) EEPROM.
3.What is the functioning of a Flash Memory?
Explain.
4. Compare and contrast Asynchronous DRAM
and Synchronous DRAM.
1.1 Computer Types
Computer definition:
Electronic device
Converts data into information
Modern computers are digital
Two digits combine to make data
Bit/Nibble/Byte/Word etc
ASCII /Uni Code

Older computers were analog

A range of values made data
1.1 Computer Types Contd…
Computer Types:
 Desktop computers
 The most common type of computer
 Sits on the desk or floor
 Performs a variety of tasks
 Workstations
 Specialized computers
 Optimized for science or graphics
 More powerful than a desktop
 Notebook computers
 Small portable computers
 Weighs between 3 and 8 pounds
 About 8 ½ by 11 inches
 Typically as powerful as a desktop
 Tablet computers
 Newest development in portable computers
 Input is through
a pen
 Run specialized versions of office products
 1.2 Functional Units
Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Figure 1.1. Basic functional units of a computer.

Information Handled by a
Computer
Instructions/machine instructions
 Govern the transfer of information within a
computer as well as between the computer and its
I/O devices
 Specify the arithmetic and logic operations to be
performed
 Program
Data
 Used as operands by the instructions
 Source program
Encoded in binary code – 0 and 1
Memory Unit
Store programs and data
Two classes of storage
 Primary storage
 Fast
 Programs must be stored in memory while they are being
executed
 Large number of semiconductor storage cells
 Processed in words
 Address
 RAM and memory access time
 Memory hierarchy – cache, main memory
 Secondary storage – larger and cheaper
Arithmetic and Logic Unit (ALU)
Most computer operations are executed in
ALU of the processor.
Load the operands into memory – bring them
to the processor – perform operation in ALU –
store the result back to memory or retain in
the processor.
Registers
Fast control of ALU
Control Unit
All computer operations are controlled by the
control unit.
The timing signals that govern the I/O transfers
are also generated by the control unit.
Control unit is usually distributed throughout
the machine instead of standing alone.
Operations of a computer:
 Accept information in the form of programs and data through
an input unit and store it in the memory
 Fetch the information stored in the memory, under program
control, into an ALU, where the information is processed
 Output the processed information through an output unit
 Control all activities inside the machine through a control unit
The processor : Data Path and Control

Data
PC Address Register #
Register A
Instructions Bank L Address
U
Register #
Instruction Data Memory
Memory
Register #
Data

Two types of functional units:

elements that operate on data values (combinational)
 elements that contain state (state elements)
 Five Execution Steps
Step name Action for R-type Action for Memory- Action for Action for
instructions reference Instructions branches jumps

Instruction fetch IR = MEM[PC]

PC = PC + 4

Instruction decode/ register A = Reg[IR[25-21]]

fetch B = Reg[IR[20-16]]
ALUOut = PC + (sign extend (IR[15-0])<<2)

Execution, address ALUOut = A op B ALUOut = A+sign IF(A==B) Then PC=PC[31-

computation, branch/jump extend(IR[15-0]) PC=ALUOut 28]||(IR[25-
completion 0]<<2)

Memory access or R-type Reg[IR[15-11]] = Load:MDR =Mem[ALUOut]

completion ALUOut or
Store:Mem[ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] =

MDR
1.3 Basic Operational Concepts
Activity in a computer is governed by
instructions.
To perform a task, an appropriate program
consisting of a list of instructions is stored in
the memory.
Individual instructions are brought from the
memory into the processor, which executes
the specified operations.
Data to be used as operands are also stored
in the memory.
A Typical Instruction
Add LOCA, R0
Add the operand at memory location LOCA to
the operand in a register R0 in the processor.
Place the sum into register R0.
The original contents of LOCA are preserved.
The original contents of R0 is overwritten.
Instruction is fetched from the memory into
the processor – the operand at LOCA is
fetched and added to the contents of R0 – the
resulting sum is stored in register R0.
Separate Memory Access and ALU
Operation
Load LOCA, R1
Add R1, R0
Whose contents will be overwritten?
Connection Between the Processor
and the Memory Memory

MAR MDR
Control

PC R0

R1
Processor
IR

ALU
Rn - 1

n general purpose
registers

Figure 1.2. Connections between the processor and the memory.

Registers
Instruction register (IR)
Program counter (PC)
General-purpose register (R0 – Rn-1)
Memory address register (MAR)
Memory data register (MDR)
Typical Operating Steps
Programs reside in the memory through
input devices
PC is set to point to the first instruction
The contents of PC are transferred to MAR
A Read signal is sent to the memory
The first instruction is read out and loaded
into MDR
The contents of MDR are transferred to IR
Decode and execute the instruction
Typical Operating Steps (Cont’)
Get operands for ALU
 General-purpose register
 Memory (address to MAR – Read – MDR to ALU)

Perform operation in ALU

Store the result back
 To general-purpose register
 To memory (address to MAR, result to MDR –
Write)
During the execution, PC is
incremented to the next instruction
Interrupt
Normal execution of programs may be
preempted if some device requires urgent
servicing.
The normal execution of the current program
must be interrupted – the device raises an
interrupt signal.
Interrupt-service routine
Current system information backup and
restore (PC, general-purpose registers,
control information, specific information)
Bus Structures
There are many ways to connect different
parts inside a computer together.
A group of lines that serves as a connecting
path for several devices is called a bus.
Address/data/control
Bus

Structure
Single-bus

Input Output Memory Processor

Figure 1.3. Single-bus structure.

1.4 DATA REPRESENTATION
Signed Integer
3 major representations:
Sign and magnitude
One’s complement
Two’s complement
Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are
negative
Sign and Magnitude Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-3 1011 0100 +4 1 100 = - 4

1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
One’s Complement Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4

-4 1011 0100 +4 1 011 = - 4

1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
Subtraction implemented by addition & 1's
complement
Still two representations of 0! This causes some
problems
Some complexities in addition
Two’s Complement Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
like 1's comp 1101 0010
except shifted -4 1100 0011 +3 0 100 = + 4
one position
clockwise -5 1011 0100 +4 1 100 = - 4
1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7

Only one representation for 0

One more negative number than positive
number
Binary, Signed-Integer
Representations
B V alues represented
Page 28
Sign and
b3 b2b1b0 magnitude 1' s complement 2' s complement

0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations.

Addition and Subtraction – 2’s Complement
4 0100 -4 1100
+3 0011 + (-3) 1101
If carry-in to the high
order bit = 7 0111 -7 11001
carry-out then ignore
carry

if carry-in differs from 4 0100 -4 1100

carry-out then overflow
-3 1101 +3 0011
1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
2’s-Complement Add and Subtract
Operations (a) 0010 ( + 2) (b) 0100 ( + 4)
+ 0011 ( + 3) + 1010 - 6
Page 31 - 2
0101 ( + 5) 1110
(c) 1011 - 5 (d) 0111 ( + 7)
+ 1110 - 2 + 1101  - 3
1001 - 7 0100 ( + 4)
(e) 1101 - 3 1101
- 1001 - 7 + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110  - 2
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001  - 7 1001
- 1011 - 5 + 0101
1110  - 2
(i) 1001 - 7 1001
- 0001 ( + 1) + 1111
1000  - 8
(j) 0010 ( + 2) 0010
- 1101  - 3 + 0011
0101 ( + 5)

Figure 2.4. 2's-complement Add and Subtract operations.

Overflow - Add two positive numbers to get a negative
number or two negative numbers to get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001
0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow
Overflow when carry-in to the high-order bit does not equal carry out
Sign Extension
 Task:
 Given w-bit signed integer x
 Convert it to w+k-bit integer with same value
 Rule:
 Make k copies of sign bit:
 X  = xw–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0
w
X • • •
k copies of MSB

• • •

X • • • • • •
k w
Sign Extension Example

short int x = 15213;

int ix = (int) x;
short int y = -15213;
int iy = (int) y;

Decimal Hex Binary

x 15213 3B 6D 00111011 01101101
ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101
y -15213 C4 93 11000100 10010011
iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011
 1.5 The Memory System :
Some basic concepts:
Maximum size of the Main Memory
byte-addressable
CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
Some basic concepts(Contd.,)
 Measures for the speed of a memory:
 memory access time.
 memory cycle time.
 An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost
target.
 Several techniques to increase the effective
size and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
Internal organization of memory
chips
Each memory cell can hold one bit of information.
Memory cells are organized in the form of an array.
One row is one memory word.
All cells of a row are connected to a common line,
known as the “word line”.
Word line is connected to the address decoder.
Sense/write circuits are connected to the data
input/output lines of the memory chip.
 7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
decoder • • • • • • cells
A2 • • • • • •
• • • • • •
A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R /W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

1.5.1 Basic Concepts of
Semiconductor RAM memories
Static RAMs (SRAMs):
 Consist of circuits that are capable of retaining their state as
long as the power is applied.
 Volatile memories, because their contents are lost when power is
interrupted.
 Access times of static RAMs are in the range of few nanoseconds.
 However, the cost is usually high.

 Dynamic RAMs (DRAMs):

 Do not retain their state indefinitely.
 Contents must be periodically refreshed.
 Contents may be refreshed while accessing them for reading.
 SRAM Cell
 Two transistor inverters are cross connected to implement a basic
flip-flop.
 The cell is connected to one word line and two bits lines by
transistors T1 and T2
 When word line is at ground level, the transistors are turned off
and the latch retains its state
 Read operation: In order to read state of SRAM cell, the word line
is activated to close switches T1 and T2. Sense/Write circuits at
the bottom monitor the state of b and b’ 
b b

T1 T2
X Y

Word line
Bit lines
 Asynchronous DRAM’s
 Each row can store 512
RAS bytes. 12 bits to select a
row, and 9 bits to select
a group in a row. Total of
Row
address Row 4096  512 8 21 bits.
latch decoder cell array
• First apply the row
address, RAS signal
latches the row address.
Then apply the column
A20- 9  A8 - 0 Sense / Write CS
circuits address, CAS signal
R /W
latches the address.
• Timing of the memory
Column
Column
unit is controlled by a
address
latch
decoder specialized unit which
generates RAS and CAS.
• This is asynchronous
CAS D7 D0
DRAM
 •Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row
•During a Read operation, the
Row
address decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Column Read/Write contents of the cells are refreshed
address
decoder circuits & latches without changing the contents of
counter
the latches.
•Data held in the latches correspond
Clock
to the selected columns are transferred
R AS to the output.
Mode register
CAS and Data input •For a burst mode of operation,
Data output
register register
R/ W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
1.5.2 Read-Only Memory (ROM)
 SRAM and SDRAM chips are volatile:
 Lose the contents when the power is turned off.
 Many applications need memory devices to retain
contents after the power is turned off.
 For example, computer is turned on, the operating
system must be loaded from the disk into the memory.
 Store instructions which would load the OS from the disk.
 Need to store these instructions so that they will not be
lost after the power is turned off.
 We need to store the instructions into a non-volatile
memory.
 Non-volatile memory is read in the same manner as
volatile memory.
 Separate writing process is needed to place information
in this memory.
 Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memories (Contd.,)
 Read-Only Memory:
 Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory (PROM):
 Allow the data to be loaded by a user.
 Process of inserting the data is irreversible.
 Storing information specific to a user in a ROM is expensive.
 Providing programming capability to a user may be better.
 Erasable Programmable Read-Only Memory
(EPROM):
 Stored data to be erased and new data to be loaded.
 Flexibility, useful during the development phase of digital
systems.
 Erasable, reprogrammable ROM.
 Erasure requires exposing the ROM to UV light.
Read-Only Memories (Contd.,)
 Electrically Erasable Programmable Read-Only
Memory (EEPROM):
 To erase the contents of EPROMs, they have to be exposed to ultraviolet
light.
 Physically removed from the circuit.
 EEPROMs the contents can be stored and erased electrically.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the
contents of an entire block of cells.
 Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.
 Power consumption of flash memory is very low, making
it attractive for use in equipment that is battery-driven.
 Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
 1.5.3 Cache Memories
 Processor is much faster than the main memory.
 As a result, the processor has to spend much of its time waiting
while instructions and data are being fetched from the main memory.
 Major obstacle towards achieving good performance.

 Speed of the main memory cannot be increased

beyond a certain point.
 Cache memory is an architectural arrangement
which makes the main memory appear faster to
the processor than it really is.
 Cache memory is based on the property of
computer programs known as “locality of
reference”.
 Cache memories
Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred

from the main memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found
in the cache.
• At any given time, only some blocks in the main memory are held in
the cache. Which blocks in the main memory are in the cache is
determined by a “mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
Mapping functions
 Mapping functions determine how memory
blocks are placed in the cache.
 A simple processor example:
 Cache consisting of 128 blocks of 16 words each.
 Total size of cache is 2048 (2K) words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
 Three mapping functions:
 Direct mapping
 Associative mapping
 Set-associative mapping.
 Main Block 0•Block
memory j of the main memory maps to j modulo 128 of
Cache
the cache. 0 maps to 0, 129 maps to 1.
Block 1
tag
•More than one memory block is mapped onto the sam
Block 0 position in the cache.
tag
Block 1 •May lead to contention for cache blocks even if the
cache is not full.
Block 127
•Resolve the contention by allowing new block to
replace the old block, leading to a trivial replacement
Block 128
tag
Block 127
algorithm.
Block 129
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
- When a new block is brought into the cache,
Block 255 the the next 7 bits determine which cache
Tag Block Word
5 7 4 Block 256 block this new block is placed in.
- High order 5 bits determine which of the possible
Main memory address Block 257
32 blocks is currently present in the cache. These
are tag bits.
•Simple to implement but not very flexible.
Block 4095
 Main Block 0
memory
•Main memory block can be placed into any cache
Cache Block 1
tag
position.
Block 0 •Memory address is divided into two fields:
tag
Block 1 - Low order 4 bits identify the word within a block.
- High order 12 bits or tag bits identify a memory
Block 127
block when it is resident in the cache.
Block 128•Flexible, and uses cache space efficiently.
tag •Replacement algorithms can be used to replace an
Block 127 Block 129
existing block in the cache when the cache is full.
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
12 4 Block 256

Main memory address Block 257

Block 4095
 Cache
Main
memory Block 0Blocks of cache are grouped into sets.
tag Block 0 Mapping function allows a block of the main
Block 1
tag
memory to reside in any block of a specific set.
Block 1
Divide the cache into 64 sets, with two blocks per set.
tag Block 2 Memory block 0, 64, 128 etc. map to block 0, and they
tag Block 3 can occupy either of the two positions.
Block 63Memory address is divided into three fields:

Block 64 - 6 bit field determines the set number.

tag - High order 6 bit fields are compared to the tag
Block 126 Block 65
fields of the two blocks in a set.
tag
Block 127 Set-associative mapping combination of direct and
associative mapping.
Number of blocks per set is a design parameter.
Block 127 - One extreme is to have all the blocks in one set,
Tag Block Word
Block 128 requiring no set bits (fully associative mapping).
5 7 4
- Other extreme is to have one block per set, is
Block 129
Main memory address the same as direct mapping.

Block 4095
 1.5.4 Virtual memories
 Recall that an important challenge in the
design of a computer system is to provide a
large, fast memory system at an affordable
cost.
 Architectural solutions to increase the effective
speed and size of the memory system.
 Cache memories were developed to increase
the effective speed of the memory system.
 Virtual memory is an architectural solution to
increase the effective size of the memory
system.

57
Virtual memories (contd..)
 Recall that the addressable memory space depends
on the number of address bits in a computer.
 For example, if a computer issues 32-bit addresses, the addressable
memory space is 4G bytes.
 Physical main memory in a computer is generally
not as large as the entire possible addressable
space.
 Physical memory typically ranges from a few hundred megabytes to 1G
bytes.
 Large programs that cannot fit completely into the
main memory have their parts stored on secondary
storage devices such as magnetic disks.
 Pieces of programs must be transferred to the main memory from
secondary storage before they can be executed.

58
 Processor
•Memory management unit (MMU) translates
virtual addresses into physical addresses.
Virtual address
•If the desired data or instructions are in the
main memory they are fetched as described
Data MMU
previously.
•If the desired data or instructions are not in
Physical address
the main memory, they must be transferred
from secondary storage to the main memory.
Cache •MMU causes the operating system to bring
the data from the secondary storage into the
Data main memory.
Physical address

Main memory

DMA transfer

Disk storage

59
Address translation
 Assume that program and data are composed of
fixed-length units called pages.
 A page consists of a block of words that occupy
contiguous locations in the main memory.
 Page is a basic unit of information that is
transferred between secondary storage and main
memory.
 Size of a page commonly ranges from 2K to 16K
bytes.
 Pages should not be too small, because the access time of a secondary
storage device is much larger than the main memory.
 Pages should not be too large, else a large portion of the page may not
be used, and it will occupy valuable space in the main memory.

60
Address translation (contd..)
 Each virtual or logical address generated by a
processor is interpreted as a virtual page
number (high-order bits) plus an offset (low-
order bits) that specifies the location of a
particular byte within that page.
 Information about the main memory location of
each page is kept in the page table.
 Main memory address where the page is stored.
 Current status of the page.
 Area of the main memory that can hold a page is
called as page frame.
 Starting address of the page table is kept in a
page table base register.
61
Address translation (contd..)
Virtual page number generated by the
processor is added to the contents of the
page table base register.
 This provides the address of the corresponding entry in the

page table.
The contents of this location in the page table
give the starting address of the page if the
page is currently in the main memory.

62
 PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as page
+ number and offset.
PAGE TABLE
PTBR + virtual
page number provide
the entry of the page This entry has the starting location
in the page table. of the page.

Page table holds information

about each page. This includes
the starting address of the page
in the main memory. Control
bits
Page frame
in memory Page frame Offset

Physical address in main memory

63
Address translation (contd..)
 Page table entry for a page also includes some
control bits which describe the status of the
page while it is in the main memory.
 One bit indicates the validity of the page.
 Indicates whether the page is actually loaded into the main memory.
 Allows the operating system to invalidate the page without actually
removing it.
 One bit indicates whether the page has been
modified during its residency in the main
memory.
 This bit determines whether the page should be written back to the
disk when it is removed from the main memory.
 Similar to the dirty or modified bit in case of cache memory.

64
Address translation (contd..)
 A small cache called as Translation Lookaside
Buffer (TLB) is included in the MMU.
 TLB holds page table entries of the most recently accessed pages.
 Recall that cache memory holds most recently
accessed blocks from the main memory.
 Operation of the TLB and page table in the main memory is similar
to the operation of the cache and main memory.
 Page table entry for a page includes:
 Address of the page frame where the page resides in the main
memory.
 Some control bits.
 In addition to the above for each page, TLB must
hold the virtual page number for each page.

65
Address translation (contd..)
How to ensure that the interrupted task can
continue correctly when it resumes
execution?
There are two possibilities:
 Execution of the interrupted task must continue from the point
where it was interrupted.
 The instruction must be restarted.

Which specific option is followed depends on

the design of the processor.

66
1.5.5 Secondary Storage Memories
Magnetic Hard Disks

Disk

Disk drive

Disk controller
Organization of Data on a Disk

Sector 0, track 1
Sector 3, track n
Sector 0, track 0

Figure 5.30. Organization of one surface of a disk.

Access Data
Sector header
on a Disk
Following the data, there is an error-correction code
(ECC).
Formatting process
Difference between inner tracks and outer tracks
Access time – seek time / rotational delay (latency time
Data buffer/cache

Disk Controller
Seek
Read
Write
Error checking
Disk Controller
Processor Main memory

System bus

Disk controller

Disk drive Disk drive

Figure 5.31. Disks connected to the system bus.

RAID Disk Arrays
Redundant Array of Inexpensive Disks
Using multiple disks makes it cheaper for
huge storage, and also possible to improve
the reliability of the overall system.
RAID0 – data striping
RAID1 – identical copies of data on two disks
RAID2, 3, 4 – increased reliability
RAID5 – parity-based error-recovery
Optical Disks (a) Cross-section

Pit Land

Reflection Reflection

No reflection

Source Detector Source Detector Source Detector

(b) Transition from pit to land

0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0

(c) Stored binary pattern

Figure 5.32. Optical disk.

Optical Disks
CD-ROM
CD-Recordable (CD-R)
CD-ReWritable (CD-RW)
DVD
DVD-RAM
Magnetic Tape Systems
File File
mark File
mark
• •
• • 7 or 9
• • bits
• •

File gap Record Record Record Record

gap gap

Figure 5.33. Organization of data on magnetic tape.