UNIT-2

Microprocessors and
Microcontrollers and
Interfacing

1
 UNIT-II
8086 architecture, register organization, memory
segmentation, programming model, memory
Addresses, physical memory organization, signal
descriptions of 8086, timing diagrams. Addressing
modes, assembler directives, macros, instruction set
and assembly language programming of 8086, simple
programs involving logical, arithmetic expressions
and string manipulations.

2
Features
 It is a 16-bit μp.
 8086 has a 20 bit address bus can access
up to 220 memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Word size is 16 bits.
 It has multiplexed address and data bus
AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty
cycle to provide internal timing.
3
 8086 is designed to operate in two modes,
Minimum and Maximum.
 It can prefetches up to 6 instruction bytes
from memory and queues them in order to
speed up instruction execution.
 It requires +5V power supply.

 A 40 pin dual in line package.

 Address ranges from 00000H to FFFFFH

 Memory is byte addressable - Every byte has

a separate address.
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Intel 8086 Internal Architecture

5
Internal architecture of 8086

• 8086 has two blocks BIU and EU.

• The BIU handles all transactions of data and
addresses on the buses for EU.
• The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
• EU executes instructions from the instruction
system byte queue.
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• Both units operate asynchronously to
give the 8086 an overlapping instruction
fetch and execution mechanism which is
called as Pipelining. This results in
efficient use of the system bus and
system performance.
• BIU contains Instruction queue, Segment
registers, Instruction pointer, Address
adder.
• EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register,
Flag register.
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EXECUTION UNIT
• Decodes instructions fetched by the BIU
• Generate control signals,
• Executes instructions.

The main parts are:

• Control Circuitry
• Instruction decoder
• ALU
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EXECUTION UNIT – General Purpose Registers
16 bits

8 bits 8 bits

AH AL Accumulator
AX

BX
BH BL Base

CX
CH CL Count

DX DH DL
Data
SP Stack Pointer
Pointer
BP Base Pointer

SI Source Index
Index
DI Destination Index
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EXECUTION UNIT – General Purpose Registers

Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal
arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more than
10
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register)
 Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be
discussed under the BIU)
• The index registers (SI & DI) and the BX generally
default to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

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• SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI register
points to memory locations in the data segment which is
addressed by the DS register. Thus, SI is associated
with the DS in string operations.

• DI: Destination Index register

– is also required for some string operations.
– When string operations are performed, the DI register
points to memory locations in the data segment which is
addressed by the ES register. Thus, DI is associated
with the ES in string operations.

• The SI and the DI registers may also be used to access data

stored in arrays 12
EXECUTION UNIT – Flag Register
• A flag is a flip flop which indicates some conditions produced by
the execution of an instruction or controls certain operations of
the EU .
• In 8086 The EU contains
 a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
 6 flags indicates some conditions- status flags
3 flags –control Flags

U U U U O D IF T S Z U A U P U C
F F F F F F F F
Sign Auxiliary Carry
Interrupt Trap Zero Parity
Over flow Direction

U - Unused 13
EXECUTION UNIT – Flag Register

Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic
instruction
execution. S=1; negative, S=0 14
 Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

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Execution unit – Flag Register
• Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 1; the sign bit has changed
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BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)

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 THE QUEUE (Q)

• The BIU uses a mechanism known as an

instruction stream queue to implement a pipeline
architecture.

• This queue permits pre-fetch of up to 6 bytes of

instruction code. Whenever the queue of the BIU is
not full, it has room for at least two more bytes and
at the same time the EU is not requesting it to read
or write operands from memory, the BIU is free to
look ahead in the program by pre-fetching the next
sequential instruction.
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• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue,

it automatically shifts up through the FIFO to the
empty location nearest the output.

• The EU accesses the queue from the output

end. It reads one instruction byte after the other
from the output of the queue.

• The intervals of no bus activity, which may occur

between bus cycles are known as Idle state.
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Segmented Memory Physical Memory

00000
The memory in an 8086/88
based system is organized as
segmented memory.
Code segment (64KB)

The CPU 8086 is able to

Data segment (64KB)

1 MB
address 1Mbyte of memory.
Extra segment (64KB)
The Complete physically
available memory may be Stack segment (64KB)
divided into a number of logical
segments.
FFFFF

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• The size of each segment is 64 KB
• A segment is an area that begins at any location which is
divisible by 16.
• A segment may be located any where in the memory
• Each of these segments can be used for a specific
function.

– Code segment is used for storing the instructions.

– The stack segment is used as a stack and it is used to store the
return addresses.
– The data and extra segments are used for storing data byte.

* In the assembly language programming, more than one data/

code/ stack segments can be defined. But only one segment of
each type can be accessed at any time.

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• The 4 segments are Code, Data, Extra and Stack segments.
• A Segment is a 64kbyte block of memory.
• The 16 bit contents of the segment registers in the BIU
actually point to the starting location of a particular segment.
• Segments may be overlapped or non-overlapped

Advantages of Segmented memory Scheme

• Allows the memory capacity to be 1Mb although the actual addresses to
be handled are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program
in different parts (segments) of the m/y, for data and code protection.
• Permits a program and/or its data to be put into different areas of
memory each time program is executed, i.e. provision for relocation may
be done .
• The segment registers are used to allow the instruction, data or stack
portion of a program to be more than 64Kbytes long. The above can be
achieved by using more than one code, data or stack segments.
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 Memory Segmentation and Segment
registers
• In 8086/88 the processors have 4 segments
registers
• Code Segment register (CS), Data Segment
register (DS), Extra Segment register (ES) and
Stack Segment (SS) register.
• All are 16 bit registers.

• Each of the Segment registers store the upper 16

bit address of the starting address of the
corresponding segments.
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24
25
Instruction pointer & summing block
• The instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
• The IP always references the Code segment register
(CS).
• The value contained in the instruction pointer is called
as an offset because this value must be added to the
base address of the code segment, which is available in
the CS register to find the 20-bit physical address.
• The value of the instruction pointer is incremented after
executing every instruction.
• To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing
block) to the address contained in the CS , which has
been shifted four bits to the left.
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27
 • Example For Address Calculation (segment: offset)

• If the data segment starts at location 1000h and a data

reference contains the address 29h where is the actual
data?

Offset 0000 0000 0010 1001

Segment Address
0001 0000 0000 0000 0000

Required Address 0001 0000 0000 0010 1001

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29
 Pin Description of 8086
• The Microprocessor 8086 is a 16-bit CPU
available in different clock rates and packaged
in a 40 pin plastic package.

• The 8086 operates in single processor or

multiprocessor configuration to achieve high
performance. The pins serve a particular
function in minimum mode (single processor
mode) and other function in maximum mode
configuration (multiprocessor mode).

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Pin Description of 8086 (Contd…)
• The 8086 signals can be categorized in three
groups.
– The first are the signal having common
functions in minimum as well as maximum
mode.
– The second are the signals which have
special functions for minimum mode
– The third are the signals having special
functions for maximum mode.

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32
 Pin Description of 8086 (Contd…)
Vcc (pin 40) : Power
Gnd (pin 1 and 20) : Ground
AD0..AD7 , AD8..AD15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take µP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the µP immediately
terminate its present activity.
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW (BR)
HLDA (output , Active High) : Hold Ack (BG)
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt
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 Pin Description of 8086 (Contd…)
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data
DT/R’ (output) : Data Transmit/Receive.
When High, data from µP to memory
When Low, data is from memory to µP

IO/M’ (output) : If High µP access I/O Device.

If Low µP access memory

RD’ (output) : When Low, µP is performing a read operation

WR’ (output) : When Low, µP is performing a write operation

ALE (output) : Address Latch Enable , Active High

Provided by µP to latch address
When HIGH, µP is using AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines 34
 Pin Description of 8086 in Detail
Power Connections
Pin Description:
GND 1 40 VCC GND – Pin no. 1, 20
Ground
CLK – Pin no. 19 – Type I
8086
Clock: provides the basic
CLK 19 timing for the processor and
GND 20 bus controller. It is
asymmetric with a 33% duty
cycle to provide optimized
internal timing.
VCC – Pin no. 40
VCC: +5V power supply pin
35
Contd…..
Address/ Data Lines

AD14 2
39 AD15
AD13 3
AD12 4
AD11 5
AD10 6
AD9 7
AD8 8 8086
AD7 9
AD6 10
AD5 11
AD4 12
AD3 13
AD2 14
AD1 15
AD0 16
36
Contd…..
Pin Description

AD15-AD0 – Pin no. 2-16, 39 – Type I/O

Address Data bus: These lines constitute the time multiplexed

memory/ IO address (T1) and data (T2, T3, TW, T4) bus. A0 is
analogous to BHE* for the lower byte of the data bus, pins D7-
D0. It is low when a byte is to be transferred on the lower portion
of the bus in memory or I/O operations. Eight –bit oriented
devices tied to the lower half would normally use A0 to condition
chip select functions. These lines are active HIGH

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Contd…..
Address Lines
A14 2 39 A15
A13 3
A12 4
38 A16
A11 5
A10 6
37 A17
A9 7
A8 8 8086
A7 9 36 A18
A6 10
A5 11 35 A19
A4 12
A3 13
A2 14
A1 15
A0 16

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Contd…..
Description:
A19/S6, A18/S5, A17/S4, A16/S3 – Pin no. 35-38 – Type O

Address / Status: During T1 these are the four most significant

address lines for memory operations. During I/O operations these
lines are low. During memory and I/O operations, status
information is available on these lines during T2, T3, TW and T4.
The status of the interrupt enable FLAG bit (S5) is updated at the
beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as
shown.
A17/S4 A16/S3 Characteristic This information
s indicates which
0 (LOW) 0 Alternate Data relocation register is
0 1 Stack presently being used
1(HIGH) 0 Code or None for data accessing.
1 1 Data 39
Contd…..
S is 0 (LOW)
Status Pins S0-S7 Pin Description:
S 2 , S1 , S 0 - Pin no. 26, 27, 28 – Type O
38 S3
Status: active during T4, T1 and
37 S4
36 S5 T2 and is returned to the passive
35 S6
state (1,1,1) during T3 or during
34 S7
8086
28 S2 (M/I O ) TW when READY is HIGH. This
27 S1 (DT/ R ) status is used by the 8288 Bus
26
S 0 ( DEN) Controller to generate all memory
and I/O access control signals.

used to indicate the beginningAny

of achange by ,and
bus cycle or during T4 isto
the return
the passive state in T3 or TW is used to indicate the end of a 40
Contd…..
Status Details
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
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Contd…..
 S5 -- Value of
Interrupt Enable flag

S6 ----- Always low (logical) indicating 8086 is

on the bus. If it is tristated another bus
master has taken control of the system bus.

----- Used by 8087 numeric coprocessor to

S7 determine whether the CPU is a 8086 or
42
8088 Contd…..
Interrupts
Pin Description:
NMI – Pin no. 17 – Type I
8086
Non – Maskable Interrupt: an edge
triggered input which causes a type 2
NMI 17
interrupt. A subroutine is vectored to via
INTR 18 an interrupt vector lookup table located
in system memory. NMI is not maskable
internally by software. A transition from
a LOW to HIGH initiates the interrupt at
the end of the current instruction. This
input is internally synchronized.

43
Contd…..
INTR – Pin No. 18 – Type I
Interrupt Request: is a level triggered input which is
sampled during the last clock cycle of each instruction
to determine if the processor should enter into an
interrupt acknowledge operation. A subroutine is
vectored to via an interrupt vector lookup table located
in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is
internally synchronized. This signal is active HIGH.

44
Contd…..
Min mode signals

33 VCC MN/ MX

31 HOLD

30 HLDA
29 WR
28 M/I O
8086
27 DT/ R

26 DEN

25 ALE

24 INTA

45
Contd…..
Pin Description
HOLD, HLDA – Pin no. 31, 30 – Type I/O
HOLD: indicates that another master is requesting a local
bus “hold”. To be acknowledged, HOLD must be active
HIGH. The processor receiving the “hold” request will issue
HLDA (HIGH) as an acknowledgement in the middle of a T1
clock cycle. Simultaneous with the issuance of HLDA the
processor will float the local bus and control lines. After
HOLD is detected as being LOW, the processor will LOWer
the HLDA, and when the processor needs to run another
cycle, it will again drive the local bus and control lines.
The same rules as apply regarding when the local bus will
be released.
HOLD is not an asynchronous input. External
synchronization should be provided if the system can not
otherwise guarantee the setup time.
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Contd…..
WR* - Pin no. 29 – Type O
Write: indicates that the processor is performing a write memory
or write I/O cycle, depending on the state of the M/IO* signal.
WR* is active for T2, T3 and TW of any write cycle. It is active
LOW, and floats to 3-state OFF in local bus “hold acknowledge”.

M/IO* - Pin no. 28 – type O

Status line: logically equivalent to S2 in the maximum mode. It is
used to distinguish a memory access from an I/O access. M/IO*
becomes valid in the T4 preceding a bus cycle and remains valid
until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO* floats
to 3-state OFF in local bus “hold acknowledge”.

47
Contd…..
DT/R* - Pin no. 27 – Type O
Data Transmit / Receive: needed in minimum system that desires
to use an 8286/8287 data bus transceiver. It is used to control the
direction of data flow through the transceiver. Logically DT/R* is
equivalent to S1* in the maximum mode, and its timing is the same
as for M/IO*. (T=HIGH, R=LOW). This signal floats to 3-state OFF
in local bus “hold acknowledge”.

DEN* - Pin no. 26 – Type O

Data Enable: provided as an output enable for the 8286/8287 in a
minimum system which uses the transceiver. DEN* is active LOW
during each memory and I/O access and for INTA cycles. For a
read or INTA* cycle it is active from the middle of T2 until the middle
of T4, while for a write cycle it is active from the beginning of T2 until
the middle of T4. DEN* floats to 3-state OFF in local bus “hold
acknowledge”.

48
Contd…..
ALE – Pin no. 25 – Type O
Address Latch Enable: provided by the processor to latch the
address into the 8282/8283 address latch. It is a HIGH pulse
active during T1 of any bus cycle. Note that ALE is never
floated.

INTA* - Pin no. 24 – Type O

INTA* is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T2, T3 and TW of each interrupt
acknowledge cycle.

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Contd…..
 Pin Description:
RQ*/GT0*, RQ*/GT1* - Pin no.
Max mode signals 30, 31 – Type I/O
33 GND Request /Grant: pins are used
31 RQ/ GT0 by other local bus masters to
30 RQ/ GT1 force the processor to release
29 LOCK the local bus at the end of the
8086 28 S2 processor’s current bus cycle.
27 S1 Each pin is bidirectional with
26 S0 RQ*/GT0* having higher priority
than RQ*/GT1*. RQ*/GT* has an
25 QS0
internal pull up resistor so may
24 QS1
be left unconnected. The
request/grant sequence is as
follows: 50
Contd…..
1. A pulse of 1 CLK wide from another local bus master
indicates a local bus request (“hold”) to the 8086 (pulse 1)
2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the
8086 to the requesting master (pulse 2), indicates that the
8086 has allowed the local bus to float and that it will enter
the “hold acknowledge” state at the next CLK. The CPU’s
bus interface unit is disconnected logically from the local
bus during “hold acknowledge”.
3. A pulse 1 CLK wide from the requesting master indicates to
the 8086 (pulse 3) that the “hold” request is about to end
and that the 8086 can reclaim the local bus at the next CLK.

51
Contd…..
Each master-master exchange of the local bus is a sequence of
3 pulses. There must be one dead CLK cycle after each bus
exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory
cycle, it will release the local bus during T 4 of the cycle when all
the following conditions are met:
 Request occurs on or before T 2.
 Current cycle is not the low byte of a word (on an odd
address)
 Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
 A locked instruction is not currently executing.

52
Contd…..
LOCK* - Pin no. 29 – Type O
LOCK* : output indicates that other system bus masters are not to
gain control of the system bus while LOCK* is active LOW. The
LOCK* signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the next instruction. This signal
is active LOW, and floats to 3-state OFF in “hold acknowledge”.
QS1, QS0 – Pin no. 24, 25 – Type O
Queue Status: the queue status is valid during the CLK cycle after
which the queue operation is performed.
QS1 and QS0 provide status to allow external tracking of the internal
8086 instruction queue.

53
Contd…..
QS1 QS0 Characteristics
0(LOW) 0 No operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent byte from Queue

54
Contd…..
Common Signals

55
Contd…..
Pin Description:

RD* - Pin no. 34, Type O

Read: Read strobe indicates that the processor is performing a
memory of I/O read cycle, depending on the state of the S2 pin. This
signal is used to read devices which reside on the 8086 local bus.
RD* is active LOW during T2, T3 and TW of any read cycle, and is
guaranteed to remain HIGH in T2 until the 8086 local bus has
floated.
This signal floats to 3-state OFF in “hold acknowledge”.

READY – Pin no. 22, Type I

READY: is the acknowledgement from the addressed memory or
I/O device that it will complete the data transfer. The READY signal
from memory / IO is synchronized by the 8284A Clock Generator to
form READY. This signal is active HIGH. The 8086 READY input
is not synchronized. Correct operation is not guaranteed if the setup
56
Contd…..
and hold times are not met.
TEST* - Pin No 23 – Type I
TEST* : input is examined by the “Wait” instruction. If the TEST*
input is LOW execution continues, otherwise the processor waits in
an “idle” state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.

RESET – Pin no. 21 – Type I

Reset: causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock
cycles. It restarts execution, as described in the instruction set
description, when RESET returns LOW. RESET is internally
synchronized.

57
Contd…..
BHE*/S7- Pin No. 34 – Type O
Bus High Enable / Status: During T1 the Bus High Enable signal
(BHE*) should be used to enable data onto the most significant half
of the data bus, pins D15-D8. Eight bit oriented devices tied to the
upper half of the bus would normally use BHE* to condition chip
select functions. BHE* is LOW during T1 for read, write, and
interrupt acknowledge cycles when a byte is to be transferred on the
high portion of the bus. The S7 status information is available during
T2, T3 and T4. The signal is active LOW and floats to 3-state OFF in
“hold”. It is LOW during T1 for the first interrupt acknowledge cycle.

BHE* A0 Characteristics

0 0 Whole word
0 1 Upper byte from / to odd address
1 0 Lower byte from / to even address
1 1 None
58
Contd…..
MN/MX* - Pin no. 33 – Type - I
Minimum / Maximum: indicates what mode the processor is to
operate in.

If the local bus is idle when the request is made the two possible
events will follow:
 Local bus will be released during the next clock.
 A memory cycle will start within 3 clocks. Now the four
rules
for a currently active memory cycle apply with condition
number 1 already satisfied.

59
Contd…..
General Bus Operation- Timing Diagrams
• The 8086 has a combined address and data bus
commonly referred as a time multiplexed address
and data bus.

• The main reason behind multiplexing address and

data over the same pins is the maximum utilization
of processor pins and it facilitates the use of 40 pin
standard DIP package.

• The bus can be demultiplexed using a few latches

and transceivers, when ever required.
60
 General Bus Operation (Contd…)
• Basically, all the processor bus cycles consist of at
least four clock cycles. These are referred to as T1, T2,
T3, and T4. The address is transmitted by the
processor during T1. It is present on the bus only for
one cycle.
• The negative edge of this ALE pulse is used to
separate the address and the data or status
information. In maximum mode, the status lines S0, S1
and S2 are used to indicate the type of operation.
• Status bits S3 to S7 are multiplexed with higher order
address bits and the BHE signal. Address is valid
during T1 while status bits S3 to S7 are valid during T2
through T4.
61
General Bus Operation

62
Addressing Modes of 8086

Addressing modes help us to understand the types of

operands and the way they are accessed while
executing an instruction.
Types of addressing mode in 8086
1. Immediate addressing mode

2. Direct addressing mode

3. Register addressing mode

4. Register Indirect addressing mode

5. Indexed addressing mode

6. Register relative addressing mode

7. Base plus index addressing mode

8. Base relative plus index addressing mode

1: Immediate addressing mode
• In this type of mode, immediate data is part of
instruction and appears in the form of successive
byte or bytes

10 ABH

MOV AX,10ABH AX
2: Direct addressing mode
• In this type of addressing mode a 16-bit memory address
is directly specified in the instruction as a part of it.

Memory
22 5000
33 5001
MOV AX,[5000H] 5002

AX
3: Register addressing mode
• In this type of addressing mode, the data is stored in the
register and it can be a 8-bit or 16-bit register. All the
registers, except IP, may be used in this mode.

10 AB BX
MOV AL,BLH BH BL
MOV AX,BXH FF 33 AX
AH AL
4: Register Indirect addressing
mode
• The address of the memory location which contains
data or operand is determined in a indirect way,
using the offset register.
Memory
22 5000
AX
33 5001

MOV AX,[BX] 5002

BX
50 00
Reflection Spot
MOV [7000H],CX
Q) Which addressing does instruction above
belong, and why?
Reflection Spot
MOV [7000H],CX
Q) Which addressing does instruction above
belonging and why?
Memory
Ans) Direct addressing mode 22 7000
33 7001
7002

CX 43 56
5: Indexed addressing mode
• In this addressing mode, offset of the operand is
stored in one of the index registers. DS is the default
segment for index register SI and DI.
Memory
22 5000
AX
33 5001
MOV AX,[SI] 5002

50 00 SI
6: Register relative addressing mode
• In this mode, the data is available at an effective
address formed by adding an 8-bit or 16-bit displacement
with the content of any one of the registers BX, BP, SI
and DI in the default (either DS or ES) segment.
Memory
44 5051
AX
33 5052

MOV AX, 50H[BX] 5053

50 00 + 50H = 5050H
Final
Index
BX Offset Address
7: Base plus index addressing
mode
• In this mode the effective address is formed by
adding content of a base register (any one of BX or
BP) to the content of an index register (SI or DI).
Default segment register DS.
12 3000
AX
MOV AX, [BX] [SI] 34 3001
3002

10 00 + 20 00 = 3000H
Final
BX SI Index
Address
8: Base relative plus index addressing
mode
• In the effective address is formed by adding an 8 or
16-bit displacement with sum of contents of any one
of the base registers (BX or BP) and any one of the
index registers, in a default segment.
12 3050
MOV AX,50H[BX][SI] AX
34 3051
3052

50H + 10 00 20 00 = 3050H
Final
BX SI Index
Address
Addressing Modes for control transfer instructions:
1. Intersegment
• Intersegment direct
• Intersegment indirect
2. Intrasegment
• Intrasegment direct
• Intrasegment indirect
1. Intersegment direct:
In this mode, the address to which the control is to be
transferred is in a different segment. This addressing mode
provides a means of branching from one code segment to
another code segment. Here, the CS and IP of the destination
address are specified directly in the instruction.
Example: JMP 5000H, 2000H;
Jump to effective address 2000H in segment 5000H.
75
2. Intersegment indirect:
In this mode, the address to which the control is to be
transferred lies in a different segment and it is passed to the
instruction indirectly, i.e. contents of a memory block containing
four bytes, i.e. IP(LSB), IP(MSB), CS(LSB) and CS(MSB)
sequentially. The starting address of the memory block may be
referred using any of the addressing modes, except immediate
mode.
Example: JMP [2000H].
Jump to an address in the other segment specified at
effective address 2000H in DS.
3. Intrasegment direct mode:
In this mode, the address to which the control is to be transferred
lies in the same segment in which the control transfers instruction lies and
appears directly in the instruction as an immediate displacement value. In
this addressing mode, the displacement is computed relative to the content
of the instruction pointer. 76
Example: JMP SHORT LABEL.
4. Intrasegment indirect mode:
In this mode, the displacement to which the
control is to be transferred is in the same segment in which
the control transfer instruction lies, but it is passed to the
instruction directly. Here, the branch address is found as
the content of a register or a memory location.
This addressing mode may be used in unconditional
branch instructions.
Example: JMP [BX]; Jump to effective address
stored in BX

77
 Macros

Macro is a set of instruction and the programmer can use it

anywhere in the program by using its name. It is mainly used to
achieve modular programming. So same set of instructions can
be used multiple times when ever required by the help of macro.
Wherever macro’s identifier is used, it is replaced by the actual
defined instructions during compilation thereby no calling and
return occurs.
%macro macro_name number_of_parameters
<macro body>
%endmacro

78
79
80
Instruction set of
8086 Microprocessor

81
Software

• The sequence of commands used to tell a microcomputer what to

do is called a program,
• Each command in a program is called an instruction
• 8088 understands and performs operations for 117 basic
instructions
• The native language of the IBM PC is the machine language of the
8088
• A program written in machine language is referred to as machine
code
• In 8088 assembly language, each of the operations is described by
alphanumeric symbols instead of 0-1s.

ADD AX, BX

(Opcode) (Destination operand) (Source operand )

82
Instructions
LABEL: INSTRUCTION ; COMMENT
Address identifier Does not generate any machine code

• Ex. START: MOV AX, BX ; copy BX into AX

• There is a one-to-one relationship between assembly and

machine language instructions

• A compiled machine code implementation of a program

written in a high-level language results in inefficient code
– More machine language instructions than an assembled version of an
equivalent handwritten assembly language program

83
Data Transfer Instructions - MOV
Mnemonic Meaning Format Operation Flags affected
MOV Move Mov D,S (S)  (D) None

Destination Source
Memory Accumulator
Accumulator Memory
NO MOV
Register Register
Memory Memory
Register Memory Immediate Segment Register
Memory Register Segment Register Segment Register
Register Immediate
Memory Immediate
Seg reg Reg 16
Seg reg Mem 16
Reg 16 Seg reg
Memory Seg reg EX: MOV AL, BL 84
Data Transfer Instructions - XCHG

Mnemonic Meaning Format Operation Flags affected

XCHG Exchange XCHG D,S (S) (D) None

Destination Source
Accumulator Reg 16 Example: XCHG [1234h], BX

Memory Register

Register Register
Register Memory NO XCHG
MEMs
SEG REGs

85
Data Transfer Instructions – LEA, LDS, LES
Mnemo Meaning Format Operation Flags
nic affected
LEA Load LEA Reg16,EA EA  (Reg16) None
Effective
Address
LDS Load LDS Reg16,MEM32 (MEM32)  (Reg16) None
Register
And DS
(Mem32+2)  (DS)

LES Load LES Reg16,MEM32 (MEM32)  (Reg16) None

Register
and ES
(Mem32+2)  (DS)

LEA SI DATA (or) MOV SI Offset DATA

86
The XLAT Instruction
Mnemonic Meaning Format Operation Flags
XLAT Translate XLAT ((AL)+(BX)+(DS)0)  (AL) None

Example:

Assume (DS) = 0300H, (BX)=0100H, and (AL)=0DH

XLAT replaces contents of AL by contents of memory location with
PA=(DS)0 +(BX) +(AL)
= 03000H + 0100H + 0DH = 0310DH
Thus
(0310DH)  (AL)
87
Arithmetic Instructions: ADD, ADC, INC, AAA, DAA

Mnemonic Meaning Format Operation Flags

affected

ADD Addition ADD D,S (S)+(D)  (D) ALL

carry  (CF)

ADC Add with ADC D,S (S)+(D)+(CF)  (D) ALL

carry carry  (CF)

INC Increment by INC D (D)+1  (D) ALL but CY

one

AAA ASCII adjust AAA If the sum is >9, AH AF,CF

for addition is incremented by 1

DAA Decimal DAA Adjust AL for decimal ALL

adjust for Packed BCD
addition

88
Examples:

Ex.1 ADD AX,2

ADC AX,2

Ex.2 INC BX
INC WORD PTR [BX]

Ex.3 ASCII CODE 0-9 = 30-39h

MOV AX,38H ; (ASCII code for number 8)

ADD AL,39H ; (ASCII code for number 9)
AL=71h
AAA ; used for addition AH=01,
AL=07
Ex.4 AL contains 25 (packed BCD)
ADD AX,3030H ; answer to ASCII 0107
AX=3137
BL contains 56 (packed BCD) 25
+ 56
ADD AL, BL --------
DAA 7B 81

89
Arithmetic Instructions – SUB, SBB, DEC, AAS, DAS, NEG
Mnemonic Meaning Format Operation Flags
affected
SUB Subtract SUB D,S (D) - (S)  (D) All
Borrow  (CF)
SBB Subtract SBB D,S (D) - (S) - (CF)  (D) All
with
borrow
DEC Decrement DEC D (D) - 1  (D) All but CF
by one
NEG Negate NEG D All

DAS Decimal DAS Convert the result in AL to All

adjust for packed decimal format
subtraction
AAS ASCII AAS (AL) difference CY,AC
adjust for (AH) dec by 1 if borrow
subtraction
90
Examples: DAS

MOV BL, 28H

MOV AL, 83H
SUB AL,BL ; AL=5BH
DAS ; adjust as AL=55H

MOV AX, 38H

SUB AL,39H; AX=00FF
AAS ; AX=FF09 ten’s complement of -1 (Borrow one from AH )
OR AL,30H ; AL=39

91
Multiplication and Division

92
Logical Instructions
Mnemonic Meaning Format Operation Flags Affected
AND Logical AND AND D,S (S) · (D) → (D) OF, SF, ZF, PF,
CF
OR Logical Inclusive OR D,S (S)+(D) → (D) AF undefined
OR OF, SF, ZF, PF,
CF
XOR Logical Exclusive XOR D,S (S) + (D)→(D) AF undefined
OR OF, SF, ZF, PF,
_ CF
NOT LOGICAL NOT NOT D (D) → (D) AF undefined
None

Destination Source
Destination
Register Register
Register Memory Register
Memory Register Memory
Register Immediate
Memory Immediate
Accumulator Immediate

93
Shift and Rotate Instructions
SHR/SAL: shift logical left/shift
arithmetic left
 SHR: shift logical right
 SAR: shift arithmetic right
 ROL: rotate left
 ROR: rotate right
 RCL: rotate left through carry
 RCR: rotate right through carry

94
 Shift Instructions
Mnemo Meaning Format Operation Flags
-nic Affected
SAL/ Shift SAL/SHL D, Count Shift the (D) left by the CF,PF,SF,ZF
SHL arithmetic number of bit positions AF undefined
Left/shift equal to count and fill the OF undefined
Logical left vacated bits positions on if count ≠1
the right with zeros

Shift the (D) right by the CF,PF,SF,ZF

SHR Shift SHR D, Count number of bit positions AF undefined
logical equal to count and fill the OF undefined
right vacated bits positions on if count ≠1
the left with zeros

Shift the (D) right by the CF,PF,SF,ZF

Shift SAR D, Count number of bit positions AF undefined
SAR arithmetic equal to count and fill the OF undefined
right vacated bits positions on if count ≠1
the left with the original
most significant bit 95
96
SHL Instruction
• The SHL (shift left) instruction performs a logical left shift
on the destination operand, filling the lowest bit with 0.

• Operand types:
SHL reg,imm8
SHL mem,imm8
SHL reg,CL
SHL mem,CL 97
Fast Multiplication
Shifting left 1 bit multiplies a number by 2
mov dl,5

shl dl,1

Shifting left n bits multiplies the operand by

2n
For example,
mov dl,5 5 * 2 2
= 20
shl dl,2 ; DL = 20
98
SHR Instruction
• The SHR (shift right) instruction performs a logical
right shift on the destination operand. The highest bit
position is filled with a zero.

Shifting right n bits divides the operand by 2n

MOV DL,80
SHR DL,1 ; DL = 40
SHR DL,2 ; DL = 10
99
SAR Instruction

• SAR (shift arithmetic right) performs a right

arithmetic shift on the destination operand.

An arithmetic shift preserves the number's sign.

MOV DL,-80
SAR DL,1 ; DL = -40
SAR DL,2 ; DL = -10
100
Rotate Instructions
Mnem Meaning Format Operation Flags Affected
-onic
ROL Rotate ROL D,Count Rotate the (D) left by the CF
Left number of bit positions equal OF undefined
to Count. Each bit shifted out if count ≠ 1
from the left most bit goes back
into the rightmost bit position.
ROR Rotate ROR D,Count Rotate the (D) right by the CF
Right number of bit positions equal OF undefined
to Count. Each bit shifted out if count ≠ 1
from the rightmost bit goes
back into the leftmost bit
position.
RCL Rotate RCL D,Count Same as ROL except carry is CF
Left attached to (D) for rotation. OF undefined
through if count ≠ 1
Carry
RCR Rotate RCR D,Count Same as ROR except carry is CF
right attached to (D) for rotation. OF undefined
through if count ≠ 1101
Carry
ROL Instruction
• ROL (rotate) shifts each bit to the left
• The highest bit is copied into both the Carry
flag and into the lowest bit
• No bits are lost

MOV Al,11110000b
ROL Al,1 ; AL = 11100001b

MOV Dl,3Fh
ROL Dl,4 ; DL = F3h
102
ROR Instruction
• ROR (rotate right) shifts each bit to the right
• The lowest bit is copied into both the Carry flag and
into the highest bit
• No bits are lost

MOV AL,11110000b
ROR AL,1 ; AL = 01111000b

MOV DL,3Fh
ROR DL,4 ; DL = F3h
103
 RCL Instruction
• RCL (rotate carry left) shifts each bit to the left
• Copies the Carry flag to the least significant bit
• Copies the most significant bit to the Carry flag

CF

CLC ; CF = 0
MOV BL,88H ; CF,BL = 0 10001000b
RCL BL,1 ; CF,BL = 1 00010000b
RCL BL,1 ; CF,BL = 0 00100001b
104
RCR Instruction
• RCR (rotate carry right) shifts each bit to the right
• Copies the Carry flag to the most significant bit
• Copies the least significant bit to the Carry flag

STC ; CF = 1
MOV AH,10H ; CF,AH = 00010000 1
RCR AH,1 ; CF,AH = 10001000 0
105
Flag control instructions
MNEM- MEANING OPERATION Flags
ONIC Affected
CLC Clear Carry Flag (CF)  0 CF
STC Set Carry Flag (CF)  1 CF
CMC Complement (CF)  (CF)l CF
Carry Flag
CLD Clear Direction (DF)  0
Flag SI & DI will be auto incremented while DF
string instructions are executed.
STD Set Direction (DF)  1
Flag SI & DI will be auto decremented DF
while string instructions are executed.
CLI Clear Interrupt (IF)  0 IF
Flag
STI Set Interrupt (IF)  1 IF
Flag 106
Compare Instruction, CMP
Mnemo Meaning Format Operation Flags
nic Affected

CMP Compare CMP D,S (D) – (S) is used in CF, AF, OF,
setting or resetting the PF, SF, ZF
flags

Allowed Operands
Destination Source
(D) = (S) ; ZF=0
RegisterRegister
(D) > (S) ; ZF=0, CF=0 RegisterMemory
(D) < (S) ; ZF=0, CF=1 Memory Register
RegisterImmediate
Memory Immediate
Accumulator Immediate
107
String?

• An array of bytes or words located in

memory
• Supported String Operations
– Copy (move, load)
– Search (scan)
– Store
– Compare

108
 String Instruction Basics

• Source DS:SI, Destination ES:DI

– You must ensure DS and ES are correct

– You must ensure SI and DI are offsets into DS and
ES respectively

• Direction Flag (0 = Up, 1 = Down)

– CLD - Increment addresses (left to right)

– STD - Decrement addresses (right to left)
109
String Instructions
Instruction prefixes

Prefix Used with Meaning

REP MOVS Repeat while not end of string

STOS CX ≠ 0

Repeat while not end of string

REPE/REPZ CMPS and strings are equal. CX ≠ 0
and ZF = 1
SCAS

Repeat while not end of string

REPNE/ CMPS
and strings are not equal. CX ≠
REPNZ SCAS 0 and ZF = 0 110
Instructions

Mnemo- meaning format Operation Flags

Nic effect
-ed
MOVS Move string MOVSB/ ((ES)0+(DI))  ((DS)0+(SI)) none
DS:SI MOVSW (SI)  (SI) ± 1 or 2
ES:DI (DI)  (DI) ± 1 or 2

CMPS Compare CMPSB/ Set flags as per All

string CMPSW ((DS)0+(SI)) - ((ES)0+(DI)) status
DS:SI (SI)  (SI) ± 1 or 2 flags
ES:DI (DI)  (DI) ± 1 or 2

111
 Mnemo- meaning format Operation
Nic
SCAS Scan string SCASB/ Set flags as per
AX – ES:DI SCASW (AL or AX) - ((ES)0+(DI))
(DI)  (DI) ± 1 or 2

LODS Load string LODSB/ (AL or AX)  ((DS)0+(SI))

DS:SI  AX LODSW (SI)  (SI) ± 1 or 2

STOS Store string STOSB/ ((ES)0+(DI))  (AL or A) ± 1 or 2

ES:DI  AX STOSW (DI)  (DI) ± 1 or 2

112
Branch group of instructions
Branch instructions provide lot of convenience to the
programmer to perform operations selectively, repetitively
etc.

Branch group of instructions

Conditional Uncondi- Iteration CALL Return

jumps tional instructions instructions instructions
jump

113
 A subroutine is a special segment of program that can be called for
execution from any point in a program.
 An assembly language subroutine is also referred to as a “procedure”.
 Whenever we need the subroutine, a single instruction is inserted in to
the main body of the program to call subroutine.
 To branch a subroutine the value in the IP or CS and IP must be
modified.
 After execution, we want to return the control to the instruction that
immediately follows the one called the subroutine i.e., the original
value of IP or CS and IP must be preserved.
 Execution of the instruction causes the contents of IP to be saved on
the stack. (this time (SP)  (SP) -2 )
 A new 16-bit (near-proc, mem16, reg16 i.e., Intra Segment) value
which is specified by the instructions operand is loaded into IP.
 Examples: CALL 1234H
CALL BX
CALL [BX]
114
Mnem- Meaning Format Operation Flags
onic Affected

CALL Subroutine CALL operand Execution continues from none

call the address of the
subroutine specified by
the operand. Information
required to return back to
the main program such as
IP and CS are saved on
the stack.

Operand
Near-proc
Far – proc
Memptr 16
Regptr 16
Memptr 32 115
RETURN
• Every subroutine must end by executing an instruction that returns control
to the main program. This is the return (RET) instruction.

• By execution the value of IP or IP and CS that were saved in the stack to

be returned back to their corresponding regs. (this time (SP)  (SP)+2 )

Mnem Meaning Format Operation Flags

-onic Affected
RET Return RET or Return to the main None
RET operand program by restoring IP
(and CS for far-proc). If
operands is present, it is
added to the contents of
SP.

Operand
None 116
Disp16
Loop Instructions
• These instructions are used to repeat a set of instructions several
times.
• Format: LOOP Short-Label
• Operation: (CX)  (CX)-1
• Jump is initialized to location defined by short label if CX≠0.
otherwise, execute next sequential instruction.
• Instruction LOOP works w.r.t contents of CX. CX must be
preloaded with a count that represents the number of times the
loop is to be repeat.
• Whenever the loop is executed, contents at CX are first
decremented then checked to determine if they are equal to zero.
• If CX=0, loop is complete and the instruction following loop is
executed.
• If CX ≠ 0, content return to the instruction at the label specified in
the loop instruction.
117
LOOP Instruction contd.

General format : LOOP r8 ; r8 is 8-bit signed value.

It is a 2 byte instruction.

Used for backward jump only.

Maximum distance for backward jump is only 128 bytes.

LOOP AGAIN is almost same as: DEC CX

JNZ AGAIN

LOOP instruction does not affect any flags.

118
Mnemonic meaning format Operation

LOOP Loop Loop short-label (CX)  (CX) – 1

Jump to location given by
short-label if CX ≠ 0

LOOPE/ Loop while LOOPE/LOOPZ (CX)  (CX) – 1

LOOPZ equal/ loop short-label Jump to location given by
while zero short-label if CX ≠ 0 and
ZF=1
LOOPNE/ Loop while LOOPNE/LOOPNZ (CX)  (CX) – 1
LOOPNZ not equal/ short-label Jump to location given by
loop while short-label if CX ≠ 0 and
not zero ZF=0

119
 Control flow and JUMP instructions
Unconditional Jump

Part 1
JMP AA
Unconditional JMP

Part 2
Skipped part

Part 3
AA XXXX Next instruction

JMP  unconditional jump

JMP Operand
120
Unconditional Jump

Unconditional Jump Instruction

Near Jump or Far Jump or

Intra segment Jump Inter segment Jump
(Jump within the segment) (Jump to a different segment)
Is limited to the address with in Permits jumps from one code
the current segment. It is achieved segment to another. It is
by modifying value in IP achieved by modifying CS and IP
Operands
Short label
Near label
Far label Inter Segment Jump
Memptr16
Regptr16 121
memptr32 Inter Segment Jump
Conditional Jump

Part 1

Jcc AA Conditional Jump

Part 2
NO
Skipped part
condition XXXX

YES

Part 3
AA XXXX Next instruction

122
Conditional Jump instructions

Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte

opcode followed by 1-byte signed displacement (range of –128 to
+127).

Conditional Jump Instructions

Jumps based on Jumps based on

a single flag more than one flag

123
Conditional Jump Instructions

Mnemonic : Jcc
Meaning : Conditional Jump
Format : Jcc operand
Operation : If condition is true jump to the address specified by operand.
Otherwise the next instruction is executed.
Flags affected : None

124
TYPES

Mnemonic meaning condition

JA Above CF=0 and ZF=0

JB Above or Equal CF=0

JB Below CF=1

JBE Below or Equal CF=1 or ZF=1

JC Carry CF=1

JCXZ CX register is Zero (CF or ZF)=0

JE Equal ZF=1

JG Greater ZF=0 and SF=OF

JGE Greater or Equal SF=OF

JL Less (SF XOR OF) = 1 125

Mnemonic meaning condition

JLE Less or Equal ((SF XOR OF) or ZF) = 1

JNA Not Above CF =1 or Zf=1

JNAE Not Above nor Equal CF = 1

JNB Not Below CF = 0

JNBE Not Below nor Equal CF = 0 and ZF = 0

JNC Not Carry CF = 0

JNE Not Equal ZF = 0

JNG Not Greater ((SF XOR OF) or ZF)=1

JNGE Not Greater nor (SF XOR OF) = 1

Equal
JNL Not Less SF = OF

126
Mnemonic meaning condition
JNLE Not Less nor Equal ZF = 0 and SF = OF
JNO Not Overflow OF = 0
JNP Not Parity PF = 0
JNZ Not Zero ZF = 0
JNS Not Sign SF = 0
JO Overflow OF = 1
JP Parity PF = 1
JPE Parity Even PF = 1
JPO Parity Odd PF = 0
JS Sign SF = 1
JZ Zero ZF = 1

127
Machine control instructions
HLT instruction – HALT processing
the HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only way to get the processor
out of the halt state are with an interrupt signal on the INTR pin or an interrupt
signal on NMI pin or a reset signal on the RESET input.

NOP instruction
this instruction simply takes up three clock cycles and does no
processing. After this, it will execute the next instruction. This instruction is
normally used to provide delays in between instructions.

ESC instruction
whenever this instruction executes, the microprocessor does NOP or
access a data from memory for coprocessor. This instruction passes the
information to 8087 math processor. Six bits of ESC instruction provide the
opcode to coprocessor.
when 8086 fetches instruction bytes, co-processor also picks up these
bytes and puts in its queue. The co-processor will treat normal 8086
instructions as NOP. Floating point instructions are executed by 8087 and
during this 8086 will be in WAIT.

128
Machine control instructions contd
LOCK instruction
this is a prefix to an instruction. This prefix makes sure that during
execution of the instruction, control of system bus is not taken by other
microprocessor.
in multiprocessor systems, individual microprocessors are
connected together by a system bus. This is to share the common
resources. Each processor will take control of this bus only when it needs to
use common resource.
the lock prefix will ensure that in the middle of an instruction,
system bus is not taken by other processors. This is achieved by hardware
signal ‘LOCK’ available on one of the CPU pin. This signal will be made
active during this instruction and it is used by the bus control logic to prevent
others from taking the bus.
once this instruction is completed, lock signal becomes inactive and
microprocessors can take the system bus.

WAIT instruction
this instruction takes 8086 to an idle condition. The CPU will not do
any processing during this. It will continue to be in idle state until TEST pin
of 8086 becomes low or an interrupt signal is received on INTR or NMI. On
valid interrupt, ISR is executed and processor enters the idle state again.
129