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03 Package

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laboudifarah6
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18 views22 pages

03 Package

Uploaded by

laboudifarah6
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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use IEEE.STD_LOGIC_ARITH.

ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
architecture behv2 of Mux is
begin
begin
-- use case statement
-- use when.. else statement
case S is
O <= I0 when S="00" else
when "00" => O <= I0;
I1 when S="01" else
when "01" => O <= I1;
I2 when S="10" else
when "10" => O <= I2;
I3 when S="11" else
when "11" => O <= I3;
"ZZZ";
when others => O <= "ZZZ";
end case;
end behv2;
end process;
end behv1;
entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;

architecture behv of DECODER is


begin

architecture when_else of DECODER is process (I)


begin begin
case I is
O <= "0001" when I = "00" else when "00" => O <= "0001";
"0010" when I = "01" else when "01" => O <= "0010";
"0100" when I = "10" else when "10" => O <= "0100";
"1000" when I = "11" else when "11" => O <= "1000";
"XXXX"; when others => O <= "XXXX";
end case;
end when_else;
end process;

end behv;
A I1
B I2
Multiplexeur S S
C
D e1 e2 e3 e4

1
A

DEMUX
B
F
C
D

S1 S0
entity ADDER is
Adder
generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);

end ADDER;
architecture behv of ADDER is

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

-- the 3rd bit should be carry

result <= ('0' & A)+('0' & B);


sum <= result(n-1 downto 0);
carry <= result(n);

end behv;
multiplier

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- two 4-bit inputs and one 8-bit outputs

entity multiplier is
port( num1, num2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0)
);
end multiplier;
architecture behv of multiplier is
begin

process(num1, num2)
variable num1_reg: std_logic_vector(2 downto 0);
variable product_reg: std_logic_vector(5 downto 0);

begin
num1_reg := '0' & num1;
product_reg := "0000" & num2;

for i in 1 to 3 loop
if product_reg(0)='1' then
product_reg(5 downto 3) := product_reg(5 downto 3)
+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := '0' & product_reg(5 downto 1);
end loop;

product <= product_reg(3 downto 0);


end process;

end behv;
register

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg is

generic(n: natural :=2);


port( I: in std_logic_vector(n-1 downto 0);
clock: in std_logic;
load: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end reg;
architecture behv of reg is

signal Q_tmp: std_logic_vector(n-1 downto 0);

begin

process(I, clock, load, clear)


begin

if clear = '0' then


-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;

end process;

-- concurrent statement
Q <= Q_tmp;

end behv;

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