Princess Sumaya Univ.

Computer Engineering Dept.

Chapter 3:
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Karnaugh Map
 Adjacent Squares
● Number of squares = number of combinations
♦ Each square represents a minterm
♦ 2 Variables  4 squares
♦ 3 Variables  8 squares
♦ 4 Variables  16 squares

● Each two adjacent squares differ in one variable

♦ Two adjacent minterms can be combined together

Example: F = x y + x y’
= x ( y + y’ )
=x 2 / 50
Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Two-variable Map

x y Minterm
m0 m1
0 0 0 m0 xy
1 0 1 m1 xy m2 m3
2 1 0 m2 xy
3 1 1 m3 xy
y
x 0 1
Note: adjacent squares 0 xy xy
horizontally and vertically
NOT diagonally 1 xy xy

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Two-variable Map
 Example
x y F Minterm
m0 m1
0 0 0 0 m0 xy
1 0 1 0 m1 xy m2 m3
2 1 0 0 m2 xy
3 1 1 1 m3 xy
y
y x 0 1

0 0 0 xy xy

x 0 1 1 xy xy
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Two-variable Map
 Example
x y F Minterm
m0 m1
0 0 0 0 m0 xy
1 0 1 1 m1 xy m2 m3
2 1 0 1 m2 xy
3 1 1 1 m3 xy
y
y x 0 1
F x y  x y  x y
0 1 0 xy xy
( x  x) y x ( y  y )
x 1 1 1 xy xy
F y  x
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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Three-variable Map

x y z Minterm m0 m1 m3 m2
0 0 0 0 m0 xyz
m4 m5 m7 m6
1 0 0 1 m1 xyz
2 0 1 0 m2 x yz
yz
3 0 1 1 m3 x yz x 00 01 11 10
4 1 0 0 m4 xyz
0 x yz x yz x yz x yz
5 1 0 1 m5 xyz
6 1 1 0 m6 xyz 1 xyz xyz xyz xyz

7 1 1 1 m7 xyz
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Three-variable Map
 Example m0 m1 m3 m2
x y z F Minterm m4 m5 m7 m6
yz
0 0 0 0 0 m0 x y z
x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 1 m2 x y z
1 xyz xyz xyz xyz
3 0 1 1 1 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 1 m5 x y z 0 0 1 1

6 1 1 0 0 m6 x y z x 1 1 0 0
7 1 1 1 0 m7 x y z z
F xy  xy
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Three-variable Map
 Example m0 m1 m3 m2
x y z F Minterm m4 m5 m7 m6
yz
0 0 0 0 0 m0 x y z
x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 0 m2 x y z
1 xyz xyz xyz xyz
3 0 1 1 1 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 0 m5 x y z 0 0 1 0

6 1 1 0 1 m6 x y z x 1 0 1 1
7 1 1 1 1 m7 x y z z Extra

F  xz  yz xy
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Three-variable Map
 Example y

x y z F Minterm 0 1 1 0
0 0 0 0 0 m0 x y z x 0 1 1 0
1 0 0 1 1 m1 x y z z
F x y z  x y z  x y z  x y z
2 0 1 0 0 m2 x y z
3 0 1 1 1 m3 x y z x z ( y  y) x z ( y  y)
4 1 0 0 0 m4 x y z xz xz
z
5 1 0 1 1 m5 x y z y
6 1 1 0 0 m6 x y z 0 1 1 0
7 1 1 1 1 m7 x y z x 0 1 1 0
z 9 / 50
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Three-variable Map
 Example m0 m1 m3 m2
x y z F Minterm m4 m5 m7 m6
yz
0 0 0 0 1 m0 x y z
x 00 01 11 10
1 0 0 1 0 m1 x y z 0 x yz x yz x yz x yz
2 0 1 0 1 m2 x y z
1 xyz xyz xyz xyz
3 0 1 1 0 m3 x y z
y
4 1 0 0 1 m4 x y z
5 1 0 1 1 m5 x y z 1 0 0 1

6 1 1 0 1 m6 x y z x 1 1 0 1
7 1 1 1 0 m7 x y z z
F z  xy
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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map

m0 m1 m3 m2
w x y z Minterm
0 0 0 0 0 m0 wxyz m4 m5 m7 m6
1 0 0 0 1 m1 wxyz m12 m13 m15 m14
2 0 0 1 0 m2 wx yz
3 0 0 1 1 m3 wx yz m8 m9 m11 m10
4 0 1 0 0 m4 wxyz
m5 wxyz
yz
5 0 1 0 1
6 0 1 1 0 m6 wxyz wx 00 01 11 10
7 0 1 1 1 m7 wxyz 00 w x yz w x yz w x yz w x yz
8 1 0 0 0 m8 wx y z
9 1 0 0 1 m9 wx y z
m10 wx y z
01 w xyz w xyz w xyz w xyz
10 1 0 1 0
11 1 0 1 1 m11 wx y z
m12 wx y z
11 wxyz wxyz wxyz wxyz
12 1 1 0 0
13 1 1 0 1 m13 wx y z
14 1 1 1 0 m14 wx y z 10 wx yz wx yz wx yz wx yz
15 1 1 1 1 m15 wx y z
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
yz
 Example wx 00 01 11 10
w x y z F Minterm w x yz w x yz w x yz w x yz
00
0 0 0 0 0 1 m0 wxyz
1 0 0 0 1 1 m1 wxyz 01 w xyz w xyz w xyz w xyz
2 0 0 1 0 1 m2 wx yz 11 wxyz wxyz wxyz wxyz
3 0 0 1 1 0 m3 wx yz
4 0 1 0 0 1 m4 wxyz 10 wx y z wx y z wx yz wx yz
5 0 1 0 1 1 m5 wxyz
6 0 1 1 0 1 m6 wxyz y
7 0 1 1 1 0 m7 wxyz
8 1 0 0 0 1 m8 wx y z 1 1 0 1
9 1 0 0 1 1 m9 wx y z 1 1 0 1
x
10 1 0 1 0 0 m10 wx y z 1 1 0 1
11 1 0 1 1 0 m11 wx y z w
1 1 0 0
12 1 1 0 0 1 m12 wx y z
13 1 1 0 1 1 m13 wx y z z
14
15
1
1
1
1
1
1
0
1
1
0
m14
m15
wx y z
wx y z F  y  wz  xz
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

B
A
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

C
1 1

B
A
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

C
1

B
A
1
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

1
B
A
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

B
A 1 1
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Four-variable Map
Example
Simplify: F = A’ B’ C’ + B’ C D’ + A’ B C D’ + A B’ C’

C
1 1 1
1
B
A
1 1 1
D

F  B D  B C  A CD

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Five-variable Map
DE D DE D
BC 00 01 11 10 BC 00 01 11 10
00 m0 m1 m3 m2 00 m16 m17 m19 m18
01 m4 m5 m7 m6 01 m20 m21 m23 m22
C C
11 m12 m13 m15 m14 11 m28 m29 m31 m30
B B
10 m8 m9 m11 m10 10 m24 m25 m27 m26

E E
A=0 A=1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Five-variable Map

A=0

A=1

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Implicants

Implicant:
Gives F = 1 C

1
1 1 1
B
1 1 1
A
1
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Prime Implicants

Prime Implicant:
Can’t grow C
beyond this size
1
1 1 1
B
1 1 1
A
1
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Essential Prime Implicants

Essential Prime Not essential

Implicant: C
No other choice
1
1 1 1
B
1 1 1
A
1
D
8 Implicants
5 Prime implicants
4 Essential prime implicants 23 / 50
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Product of Sums Simplification

w x y z F F
y y
0 0 0 0 0 1 0 w
1 1 0 1 z F
1 0 0 0 1 1 0
2 0 0 1 0 1 1 0 1 x
1 0 x z
3 0 0 1 1 0 1 1 1 0 1
w
4 0 1 0 0 1 0 1 1 0 0
5 0 1 0 1 1 0 F y  w z  x z
z
6 0 1 1 0 1 0
7 0 1 1 1 0 1 y
8 1 0 0 0 1 0 F y z  w x y
9 1 0 0 1 1 0 1 1 0 1
10 1 0 1 0 0 1 1 1 0 1 F y z  w x y
11 1 0 1 1 0 1 x
1 1 0 1
12 1 1 0 0 1 0 w y
13 1 1 0 1 1 0 1 1 0 0 z
z w F
14 1 1 1 0 1 0
x
15 1 1 1 1 0 1 y
F ( y  z )  ( w  x  y )
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Don’t-Care Condition
Example A {0 1 if a quarter is deposited
otherwise

B {0 1 if a dime is deposited
otherwise

C {
1 if a nicle is deposited
0 otherwise

A B C $ Value You can only

0 0 0 $ 0.00 drop one coin at
0 0 1 $ 0.05 a time.
0 1 0 $ 0.10
0 1 1 Not possible
1 0 0 $ 0.25
1 0 1 Not possible Used as
1 1 0 Not possible “don’t care”
1 1 1 Not possible
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Don’t-Care Condition
Example A

Logic F
B
Circuit

A B C F F ( A, B, C )  (1, 4)
0 0 0 0
0 0 1 1 d ( A, B, C )  (3, 5, 6, 7)
0 1 0 0
0 1 1 x
1 0 0 1 Don’t care
1 0 1 x what value
1 1 0 x F may take
1 1 1 x
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Don’t-Care Condition
Example A

B F

0 1 x 0
A 1 x x x
C
F  A B C  AB C
F A  C
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Don’t-Care Condition
 Example F (w, x, y, z) = ∑(1, 3, 7, 11, 15)
d (w, x, y, z) = ∑(0, 2, 5)
x=0 x=1 x=0
y y

x 1 1 x x x
x=1
x 1 0 x 0
x x
1 0 0 0
w w
1 0 0 0
z z
F y z  w z F z  w y
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Universal Gates
 One Type
● Use as many as you need (quantity), but one type only.
 Perform Basic Operations
● AND, OR, and NOT
 NAND Gate
● NOT-AND functions
● OR function can be obtained from AND by Demorgan’s
 NOR Gate
● NOT-OR functions (AND by Demorgan’s)
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Universal Gates
 NAND Gate
● NOT:
A F=A

● AND: A
B F=A•B

● OR: DeMorgan’s

A
F=A+B
B
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Universal Gates
 NOR Gate
● NOT: A F=A

● OR: A F=A+B
B

● AND: DeMorgan’s

A
F=A•B
B
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
NAND & NOR Implementation
 Two-Level Implementation
A A A
B B B
F F F
C C C
D D D

A A
B B
F F
C C
D D

B
F
C

D
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
NAND & NOR Implementation
 Two-Level Implementation
A A A
B B B
F F F
C C C
D D D

A A
B B
F F
C C
D D

B
F
C

D
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
NAND & NOR Implementation
 Multilevel NAND Implementation
C C
D D
B B
A A
B F B F
C C

C
D
B
A
B F
C

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
NAND & NOR Implementation
 Multilevel NOR Implementation
A A
B B
A A
B F B F

C C
D D

A
B
A
B F

C
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Gate Shapes
 AND

 OR

 NAND

 NOR

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Other Implementations
 AND-OR-Invert

 OR-AND-Invert

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Implementations Summary
 Sum Of Products:
● AND-OR
● AND-OR-Invert = AND-NOR = NAND-AND
 Products Of Sums
● OR-AND
● OR-AND-Invert = OR-NAND = NOR--OR

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Exclusive-OR
 XOR
F=xy=xy+xy
x x

F F

y y

 XNOR
F=xy=xy=xy+xy
x x

F F

y y 39 / 50
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Exclusive-OR
 Identities
●x0=x x y XOR
●x1=x 0 0 0
0 1 1
●xx=0
1 0 1
●xx=1 1 1 0
●xy=xy=xy
 Commutative & Associative
●xy=yx
●(xy)z=x(yz)=xyz

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Exclusive-OR Functions
 Odd Function x y z XOR XNOR

F=xyz 0 0 0 0 1
0 0 1 1 0
F = ∑(1, 2, 4, 7) 0 1 0 1 0
x 0 1 1 0 1
y F 1 0 0 1 0
z
1 0 1 0 1
 Even Function 1 1 0 0 1
1 1 1 1 0
F=xyz
yz
F = ∑(0, 3, 5, 6) x 00 01 11 10
x 0 0 1 0 1
y F
z 1 1 0 1 0

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Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Parity

1 1
0 0
1
0
0 0

1 1
0 0
1
0
0
0
1 1

Parity Parity
Generator Checker
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Parity Generator
 Odd Parity
1 1
0 0
1 1
0 0

1
Odd number of ‘1’s

 Even Parity
1 1
0 0
1 1
0 0

0
Even number of ‘1’s

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Parity Checker
 Odd Parity
1
0
1
0

Error
1
Check
 Even Parity
1
0
1
0

Error
0 Check

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
 Mano
● Chapter 3
♦ 3-1
♦ 3-3
♦ 3-5
♦ 3-7
♦ 3-9
♦ 3-15
♦ 3-16
♦ 3-18
♦ 3-22
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
 Mano
3-1 Simplify the following Boolean functions, using three-
variable maps:
(a) F (x, y, z) = ∑(0, 2, 6, 7)
(b) F (A, B, C) = ∑(0, 2, 3, 4, 6)
(c) F (a, b, c) = ∑(0, 1, 2, 3, 7)
(d) F (x, y, z) = ∑(3, 5, 6, 7)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
3-3 Simplify the following Boolean functions, using three-
variable maps:
(a) xy + x’y’z’ + x’yz’ (b) x’y’ + xz + x’yz’
(c) A’B + BC’ + B’C’

3-5 Simplify the following Boolean functions, using four-

variable maps :
(a) F (w, x, y, z) = ∑(1, 4, 5, 6, 12, 14, 15)
(b) F (A, B, C, D) = ∑(0, 1, 2, 4, 5, 7, 11, 15)
(c) F (w, x, y, z) = ∑(2, 3, 10, 11, 12, 13, 14, 15)
(d) F (A, B, C, D) = ∑(0, 2, 4, 5, 6, 7, 8, 10, 13, 15)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
3-7 Simplify the following Boolean functions, using four-
variable maps:
(a) w’z + xz + x’y + wx’z (b) B’D + A’BC’ + AB’C +
ABC’
(c) AB’C + B’C’D’ + BCD + ACD’ + A’B’C + A’BC’D
(d) wxy + yz + xy’z + x’y
3-9 Find the prime implicants for the following Boolean
functions, and determine which are essential:
(a) F (w, x, y, z) = ∑(0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
(b) F (A, B, C, D) = ∑(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c) F (A, B, C, D) = ∑(1, 3, 4, 5, 10, 11, 12, 13, 14, 15)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
3-15 Simplify the following Boolean function F, together with
the don’t-care conditions d, and then express the
simplified function in sum of products:
(a) F (x, y, z) = ∑(0, 1, 2, 4, 5)
d (x, y, z) = ∑(3, 6, 7)
(b) F (A, B, C, D) = ∑(0, 6, 8, 13, 14)
d (A, B, C, D) = ∑(2, 4, 10)
(c) F (A, B, C, D) = ∑(1, 3, 5, 7, 9, 15)
d (A, B, C, D) = ∑(4, 6, 12, 13)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
3-16 Simplify the following expressions, and implement them
with two-level NAND gate circuits:
(a) AB’ + ABD + ABD’ + A’C’D’ + A’BC’
(b) BD + BCD’ + AB’C’D’

3-18 Draw a logic diagram using only two-input NAND gates

to implement the following expression:
(AB + A’B’) (CD’ + C’D)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering
Dept.
Homework
3-22 Convert the logic diagram of the circuit shown in Fig. 4-4
into a multiple-level NAND circuit.
z

D
C y

B
x

A w

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