Simulation using

ModelSim
Course: COEN 6501
Prepared by: Rokibul Hasan Bhuiyan

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 For Scientific Linux Kernel in Lab
• Open Xterm
• To connect to server.
ssh –X (your encs user name)@login.encs.Concordia.ca

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 Objective: We will simulate a half-adder circuit using structural VHDL in ModelSim

Things we have to look for:

Components of the circuit ( in this case and gate, xor gate would be our component)

Fig: Half-Adder circuit

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Start ModelSim on your computer

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• Go to file menu
• Move your cursor to New
• Select project…

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This window will pop up.
• Fill Project Name
• Fill Library name if you want to change
the name or it can be kept as work by default
• Click OK

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• Click Create New File

• If you have the files

already then click on
Add Existing File
and select the directory
or files you want to add

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• Put File Name
• Click OK

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I am adding a Xor gate to
project as I am building a half
adder which has xor gate as
component

**avoid naming file as

xor,and,or only as they are
library functions. We can use
And_1,xor_2 as names

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If you click twice on the file then
a notepad will show up in the right Write your code here
where we have to write the code

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 Can click on this icon to compile

or

You can right click on file name

And select “compile Selected” option

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• If you haven’t saved
the file you will get this
window to save your
changes before
compiling.
• It is a good practice to
save the file after
every change.
• Click Yes

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We have some errors in code.
So, the compiler could not compile.

Click on this line twice to see errors in code

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Here you can see the list of errors

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Status

Correct them and compile again.

You will get successful message in your
Transcript window and also a green tick mark in status.

Transcript

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 Now we are going to add component and gate
You can along with main file Half adder.
also use
this button
to add new
file

Right Click here in blank space and

select “Add to project” and then “New
File…” or “Existing File”

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We have added and gate
following the same
procedure for xor gate

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 You can use this
button to compile all
files in project or
follow the procedure
how you have
compiled xor_2 file .
Just select “compile
all” option.

We have added half adder file and compile all

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 Click on this one to go to
You can also use
Start simulation window
Simulate
To go to Start
simulation window

1.Expand the library

2. Choose the file you

want to simulate and
click OK

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Alternative method to simulate or page 18 is in next page

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 2. Select the file and double click

1. Click here to open library directly

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 You can see input output of the design

This window will pop-up

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1.Right click on the file name “half_adder_structural”
2.Add
3. To wave
4.All items in region
Now we have added all the input and outputs in the waveshape

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 This one run the simulation for all the
test cases if you have a testbench.
This one is the
This one will run the
simulation time. You
simulation for
can change it
specified time cycle
such as 200ns which is
written in simulation
time.

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 Right Click
here on “0”
to get this
options
Now we would give
some input values
to see output using
“Force..” option

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• Change the value. I am changing it to “1”.
• Press OK

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Input Current value on 113 ns
and
outputs • So I have forced value of a to
be 1 and value of b to be 0.
Then I run it for 200ns .
• We can see that the output we
got are sum=1 and cry=0.

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 • So I have forced value of a to
be 1 and value of b to be 1.
Click anywhere in Then I run it for 200ns .which
this space to see will start from 201 ns and
the input output finish at 400ns.
values for that • We can see that the output we
time. got are sum=0 and cry=1 for
that cycle.
• So it is supporting truth table
of half adder circuit

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Further Reading: How to use testbench to simulate half adder circuit

Contact: [email protected]

Ref:
1. https://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/L7_Slides.pdf
2. https://upload.wikimedia.org/wikipedia/commons/thumb/d/d9/Half_Adder.svg/1920px-Half_Adder.svg.png

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