19ECE204

Digital Electronics and Systems

III Semester
B. Tech. (ECE & CSE)
Amrita School of Engineering, Bengaluru

Arithmetic Circuits

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 Unsigned Arithmetic
• Numbers that are positive only are called unsigned, and numbers that can
also be negative are called signed.
• We will deal with binary arithmetic in this course.
• Unsigned Binary Addition and Subtraction
 Binary addition is performed in the same way as decimal addition
except that the values of individual digits can be only 0 or 1.

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19ECE204/Digital Electronics & Systems, III Semester, B. Tech. (ECE and CSE)
 Unsigned Arithmetic - Addition
• Single Digit Addition, all possible combinations

Can we get a
truth table for one
bit unsigned
addition ??

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 Unsigned Arithmetic - Half Adder
This circuit, which implements the addition of only two bits, is called a half-adder.

Logic Circuit
Truth Table

s = xy’ +
x’y
c = xy

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 Unsigned Arithmetic - Multi bit
By Hand
Method

How to design a digital circuit for

this ???

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 Unsigned Arithmetic - Multi bit

• For bit position 0, there is no carry-in, and hence the addition is the same
as Half Adder.
• For each other bit position i the addition involves bits X i and Yi, and a
carry-in Ci.
• This is a three variable function, for which truth table can be derived.

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 Unsigned Arithmetic - Full Adder
This circuit, which implements the addition of only three bits, is called
a Full-adder.
Truth Table K-map simplification

si = Ʃ m(1,2,4,7)
ci+1 = Ʃ m(3,5,6,7)

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 Unsigned Arithmetic - Full Adder

Logic Circuit
Using NAND Gates only

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Unsigned Arithmetic - Decomposed Full Adder

2 Half
Adder = 1
Full Adder

HA2 ci+1 = Ʃ m(3,5,6,7)

HA1
= xi’yici + xiyi’ci + xiyici’ + xiyici
= xi’yici + xiyi’ci + xiyi

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 Unsigned Arithmetic - Ripple Carry Adder

• To perform addition by hand, we start from the least-significant digit and

add pairs of digits, progressing to the most-significant digit.
• If a carry is produced in position i, then this carry is added to the
operands in position i + 1.
• The same arrangement can be used in a logic circuit that performs
addition.

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Unsigned Arithmetic - Ripple Carry Adder

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 Unsigned Arithmetic - Ripple Carry Adder

• When the operands X and Y are applied as inputs to the adder, it takes
some time before the output sum, S, is valid.
• Each full-adder introduces a certain delay before its S i and Ci+1 outputs are
valid Let this delay be denoted as △t
• Thus the carry-out from the first stage, C 1 arrives at the second stage △t
after the application of the x0 and y0 inputs. The carry-out from the
second stage, C2, arrives at the third stage with a 2△t delay, and so on
• The signal Cn-1 is valid after a delay of (n - 1)△t, which means that the
complete sum is available after a delay of n△t.

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 Unsigned Arithmetic - Design Example

• Design a multiplier that multiplies an eight bit unsigned number by 3.

P = 3A where A is 8-bit unsigned number.
A = a7a6…a0
P = p7p6 …p0
3A = A + A + A
A = a7a6…a0 8-bits
+ A = a7a6…a0 8-bits
2A = c8 s7s6…s0 9-bits
A = 0 a7a6…a0 9-bits
P = p9p8p7…….p0 10-bits

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 Unsigned Arithmetic - Design Example

Normal approach

Cin = 0

Cin = 0

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 Unsigned Arithmetic - Design Example
• Design a multiplier that multiplies an eight bit unsigned number by 3.
P = 3A where A is 8-bit unsigned number.
A = a7a6…a0 2 = 10
P = p7p6 …p0 4 = 100
3A = 2A + A 8 = 1000
A = a7a6…a0 8-bits In Binary number system
2A = a7a6…a0 0 9-bits left shift by 1-bit is equal +
A = 0a7a6…a0 9-bits to multiplied by 2

P = p9p8p7…….p0 10-bits

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 Unsigned Arithmetic - Design Example

Efficient Approach

Cin = 0

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 Fast Adders
• The performance of a large digital system is dependent on the speed of
circuits that form its various functional units.
• Obviously, better performance can be achieved using faster circuits.
• This can be accomplished by using superior (usually newer) technology in
which the delays in basic gates are reduced.
• But it can also be accomplished by changing the overall structure of a
functional unit, which may lead to even more impressive improvement.
• To reduce the delay caused by the effect of carry propagation through the
ripple-carry adder, we can attempt to evaluate quickly for each stage
whether the carry-in from the previous stage will have a value 0 or 1.
• If a correct evaluation can be made in a relatively short time, then the
performance of the complete adder will be improved.

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 Fast Adders - Carry Look Ahead Adder
• Based on Full adder circuit the carry-out function for stage i can be realized as-

Generate function

Propagate function

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 Fast Adders - Carry Look Ahead Adder
ci+1 = gi + pici
Substituting i = 0,1,2,3…..
c1 = g0 +p0c0
c2 = g1 + p1c1 = g1 + p1(g0 +p0c0) = g1 + p1g0 + p1p0c0
c3 = g2 + p2c2 = g2 + p2(g1 + p1g0 + p1p0c0)
= g2 + p2g1 + p2p1g0 + p2p1p0c0
c4 = g3 + p3c3 = g3 + p3(g2 + p2g1 + p2p1g0 + p2p1p0c0)
= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

Where g0 = x0y0 and p0 = x0 + y0

g1 = x1y1 and p1 = x1 + y1
g2 = x2y2 and p2 = x2 + y2

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 Fast Adders - Carry Look Ahead Adder
• Expanding in term of i-1 gives

• This expression represents a two-level AND-OR circuit in which C i+l is

evaluated very quickly. An adder based on this expression is called a
carry-lookahead adder.

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 Fast Adders - Carry Look Ahead Adder

Critical Path : From

x0 - y0 to c2
For any n bit adder
gate delay for carry
= 2n+1

c1 = g0 +p0c0
c2 = g1 + p1c1
Where g0 = x0y0 and p0 = x0 + y0
g1 = x1y1 and p1 = x1 + y1

Ripple Carry adder

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 Fast Adders - Carry Look Ahead Adder

Critical Path: From x0-y0 to c2

Gate Delay for c2 - 3
For n-bit adder, gate delay for
carry = 3
𝟏 ∆ 1 For n-bit adder, gate delay for
sum = 4

c1 = g0 +p0c0
c2 = g1 + p1g0 + p1p0c0
2
𝟒∆ 2 1 Where g0 = x0y0 and p0 = x0 + y0
g1 = x1y1 and p1 = x1 + y1
𝟑∆ 𝟑∆

Carry look Ahead Adder

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 Unsigned Arithmetic - Half Subtractor
• The half subtractor is a building block for subtracting two binary
numbers.
• It has two inputs and two outputs. This circuit is used to subtract two
single bit binary numbers A and B. The 'diff' and 'borrow' are two output
states of the half subtractor.

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 Unsigned Arithmetic - Full Subtractor
• The full subtractor is a combinational circuit which is used to perform
subtraction of three input bits: the minuend X, subtrahend Y and borrow
in Bin.
• The full subtractor generates two output bits: the difference D and borrow
out Bout.
Truth Table

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 Signed Number Representation

• Positive numbers are represented using the positional number

representation as explained in the previous section.
• Negative numbers can be represented in three different ways:
• Sign-and-magnitude
• 1 's complement
• 2's complement.

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Signed Number Representation- Sign Magnitude Representation

Example: Drawbacks
+5 = 0101 • Range
-5 = 1101 • Circuit complexity

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Signed Number Representation - 1’s Complement
• In a complementary number system, the negative numbers are defined
according to a subtraction operation involving positive numbers.
• In the 1's complement scheme. an n-bit negative number, K, is obtained
by subtracting its equivalent positive number, P, from 2 n-1
• K = (2 -1)-P
Example:
n

-5 = (24-1)-0101 = 1111-0101 = Simply it is

1010 complement of its
-3 = (24-1)-0011 = 1111-0011 = positive number
•
1100
To get 1’s complement of any negative binary number, simply invert
each bit of the corresponding positive number.
(+11)10 => sign-magnitude = (0 1011)2 1’s complement = (0 1011)2
(-11)10 => sign-magnitude = (1 1011)2 1’s complement = (1 0100)2

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Signed Number Representation - 2’s Complement
• In the 2's complement scheme, a negative number, K, is obtained by
subtracting its equivalent positive number, P, from 2 n
• K = 2n-P
Example:
-5 = 24-0101 = 10000-0101 =
1011 Simply it is 1’s
-3 = 24-0011 = 10000-0011 = complement plus one
1101
• To get 2’s complement of any negative binary number, add 1 to the 1’s
complement.
(+11)10 => sign-magnitude = (0 1011)2 2’s complement = (0 1011)2
(-11)10 => sign-magnitude = (1 1011)2 1’s complement = (1 0100)2
2’s complement = (1 0101)2

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Signed Number Representation

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 Signed Number Representation
• Represent (+23) in 8-bit 1’s complement format.
(+23) --> S-M = 0 0010111
1’s comp = 0 0010111
• Represent (-23) in 8-bit 1’s complement format.
(-23) --> S-M = 1 0010111
1’s comp = 1 1101000

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 Signed Arithmetic - Sign Magnitude
• If both operands have the same sign, then the addition of sign-and-
magnitude numbers is simple. The magnitudes are added, and the
resulting sum is given the sign of the operands.

• However, if the operands have opposite signs, the task becomes more
complicated. Then it is necessary to subtract the smaller number from the
larger one.

• This means that logic circuits that compare and subtract numbers are also
needed.

• For this reason, the sign-and-magnitude representation is not used in

computers.

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 Signed Arithmetic - 1’s Complement Addition
• An obvious advantage of the 1's complement representation is that a
negative number is generated simply by complementing all bits of the
corresponding positive number..

(+2) => S-M = 1’s comp =2’s comp = 0 010

(-2) => S-M =1 010,
1’s comp = 1 101,
2’s comp = 1 110
(+5) => S-M = 1’s comp =2’s comp = 0 101
(-5) => S-M =1 101,
1’s comp = 1 010,
2’s comp = 1 011

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 Signed Arithmetic - 1’s Complement Addition

Adding the extra carry

is an overhead

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Signed Arithmetic - 2’s Complement Addition

No extra addition of carry is required,

hence this is more suitable for addition
operation

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Signed Arithmetic - 2’s Complement Subtraction

Hence, Subtraction can be done by adder

itself
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 Signed Arithmetic - 2’s Complement
• Perform the following
1) (+10)10 + (-12)10
2) (+10)10 - (+15)10

1) (+10)10 + (-12)10 2) (+10) – (+15) = (+10) + (-15)

2’s comp 2’s comp
+10 0 1010 +10 0 1010
form form
2’s comp 1 0100 +(- 2’s comp 1 0001
-12
form ——— 15) form ———
2’s comp 1 1110 2’s comp 1 1011
-2 -5
form ———— form ————

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Adder and Subtractor Unit for Unsigned Numbers
• Assume two unsigned 4 bit numbers A and B where
A = 1011
B = 0110
 To perform A + B we use 4-bit Ripple carry adder where the carry in to
the full adder, which will add LSB, is 0.
 For subtraction A – B in form of addition A is added with 2’s complement
of B i.e. A + (-B)
A = 1011 A = 1011
B = 0110 (-B) = 1001 1’s comp of
+ 0c0 1 1’s comp + 1 = 2’s comp
10001 10101
Discard

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 Adder and Subtractor Unit for Unsigned Numbers
• To perform both the operation A + B and A – B with the same circuit, for
addition we need B as normal b but for subtraction we need 1’s
complement of B.
• This can be achieved if we will apply each bit of B to 2-input XOR gate
where the second input for XOR gate will be a control signal which will
be 0 for addition and 1 for subtraction.

⊕⊕⊕⊕ ⊕⊕⊕⊕
B=0 1 1 0 B=0 1 1 0

0 0 0 0 1 1
1 1
0 1 1 0 B 1 0 0
1 1’s comp of B

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Adder and Subtractor Unit for Unsigned Numbers

= 0 for addition
1 for subtraction

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 Adder and Subtractor Unit
Design minimum cost circuits to perform following operation on two 3-bit
unsigned numbers A and B-
a) A + 2B
b) A – 2B using 2’s complement
c) A ± 2B
Solution-
A = a2a1a0 -- 3 bits
B = b2 b 1 b 0 -- 3 bits
2B = b2b1b00 -- 4 bits
A = 0 a2a1a0 -- 4 bits

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 Adder and Subtractor Unit
a) A + 2B

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 Adder and Subtractor Unit
b) A – 2B using 2’s complement

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 Adder and Subtractor Unit
b) A ± 2B

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 Arithmetic Overflow
• The result of addition or subtraction is supposed to fit within the
significant bits used to represent the numbers.

• If n bits are used to represent signed numbers, then the result must be in
the range -2n- 1 to 2n- 1 - 1.

• If the result does not fit in this range, then we say that arithmetic
overflow has occurred.

• To ensure the correct operation of an arithmetic circuit, it is important to

be able to detect the occurrence of overflow.

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 Arithmetic Overflow

cn-1 - carry-out from the magnitude MSB

position cn – carry-out from the sign-bit
position 4
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 Arithmetic Overflow
• To solve the problem of arithmetic overflow we need to increase the size of
input numbers by 1-bit.
• For example (+7) + (+2)

=0⊕1=1

So arithmetic overflow exists here. To solve this we will represent (+7) and (+2)
with 5 bits.
(+7) 0 0111
+ (+2) + 0 0010
(+9) 0 1001
Now c3 = 0 and c4 = 0
Overflow = 0 ⊕ 0 = 0

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