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Lec 2 M1 RTL Verilog

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Yasser Hanafy
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11 views32 pages

Lec 2 M1 RTL Verilog

Uploaded by

Yasser Hanafy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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RTL Design using Hardware

Description Languages
Lecture 2
Verilog Examples

1
The Need for HDL’s
• In the beginning designs involved just a few gates,
and thus it was possible to verify these circuits on
paper or with breadboards

• As designs grew larger and more complex,


designers began using gate-level models
described in a Hardware Description Language to
help with verification before fabrication

2
The Need for HDL’s – Cont’d
• When designers began working on 100,000 gate
designs, these gate-level models were too low-
level for the initial functional specification and
early high-level design exploration

3
Levels of Abstraction
• Abstract behavioral models
written in an HDL provided both
a precise specification and a
framework for design
exploration.
• HDL Allows designers to talk
about what the hardware should
do without actually designing
the hardware itself, or in other
words HDLs allow designers to
separate behavior from
implementation at various levels 4
Levels of Abstraction – Cont’d

5
Advantages of HDL
• Designers can develop an executable functional
specification that documents the exact behavior of
all the components and their interfaces
• Designers can make decisions about cost,
performance, power, and area earlier in the design
process
• Designers can create tools which automatically
manipulate the design for verification, synthesis,
optimization, etc.

6
HDL is different
• Software Programming Language
• Language which can be translated into machine
instructions and then executed on a computer
• Hardware Description Language
• Language with syntactic and semantic support for
modeling the temporal behavior and spatial structure
of hardware

7
Let’s Start

8
Operands
Operand Comments
Constant Signed or Unsigned
Parameter Signed or Unsigned
Wire Scalar or Vector
Register Scalar or Vector
bit Select One bit from a Vector
Part Select Contiguous bits of a Vector
Memory Element One word of a memory

9
Constants and Parameters
Value Comment
127 Signed decimal: Value = 8-bit binary vector: 0111_1111
–1 Signed decimal: Value = 8-bit binary vector: 1111_1111
–128 Signed decimal: Value = 8-bit binary vector: 1000_0000
4'b1110 Binary base: Value = unsigned decimal 14
8'b0011_1010 Binary base: Value = unsigned decimal 58
16'h1A3C Hexadecimal base: Value = unsigned decimal 6716
6’h3E Hexadecimal base: Value = unsigned decimal …………
9'o536 Octal base: Value = unsigned decimal 350
–22 Signed decimal: Value = 8-bit binary vector: 1110_1010
8'o352 Octal base: Value = 8-bit binary vector: 1110_1010 = unsigned decimal 234

10
Operations

11
Operations

12
Operations

13
Operations

14
Operation Example

15
Module

16
Example

17
Description Types
• Structural Description
• Dataflow Description
• Behavioral Description

18
Structural Description
• List of sub-components and how they are
connected
• Just like schematics, but using text
• tedious to write, hard to decode
• You get precise control over circuit details
• May be necessary to map to special resources of
the FPGA/ASIC

19
Structural Description

20
Structural Description

21
Structural Description

22
Structural Description – Generate

23
Dataflow Description
• Register transfer level (RTL) is a combination of
dataflow modeling and behavioral modeling and
characterizes the flow of data through logic
circuits

24
Dataflow Description Example

25
Behavioral Description
• Always Statement

26
Non-Continuous Blocking Assignments

27
Case Statement

28
If Statement

29
D-Flip-Flop

30
Blocking vs Non-Blocking

31
Simplified Guidelines
• Combinational logic:
• Continuous Assignment:
assign a = b & c;
• Always block with @(*)
always @(*) begin
a = b & c; // blocking statement
end
• Sequential logic:
• Always block with @(posedge clk)
always @(posedge clk) begin
a <= b & c; // nonblocking statement
end
32

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