Transmission lines

and signal integrity

 Behavior of Electrical Circuit at DC and low frequency

(Faraday’s law)

Sum of the product of the electric field and length (E.dL) around a
closed loop, i.e., the total voltage obtained = time-rate-of-change of
the magnetic flux passing through that closed path

Applying Faraday’s law for the below circuit:

If there are no time-varying quantities (i.e. the magnetic flux density

is constant and circuit doesn't move), then
(Nothing but KVL)
• Faraday’s law and KVL
– At DC and low frequency EMF within an element is static or quasi-
static, i.e., do not vary with time within the element
– Thus, E and H are de-coupled. As a result,
– For a static field,
or

– In other words, sum of the potential drops in a closed circuit = 0, (KVL)

=0
• Conservation of charge
– Rate of change in charge is due to charge being taken out by the
current flowing

Divergence
theorem

V
S (bounded surface)

• Continuity eqn. and KCL Point form

– For static case, or (Divergence theorem)

,which may be written as

– i.e., sum of the currents flowing out of a circuit node is zero

 Differences in analyzing low and high frequency circuits

• In electronic systems at low frequency,

1. Current is delivered through wire connecting the lumped components
2. Power is transferred through the wire
3. Applied source affects current and voltage everywhere instantly
4. This is because electrical length of components, de 

• As frequency increases,  decreases and

1. Current is confined to the surface of the conductor due to skin depth
2. Components become comparable to 
3. Power transfer happens through electric and magnetic fields guided in the
system through a transmission line
4. Thus, current and voltage waves in a transmission line vary in the circuit and
affects the circuit differently
5. Transmission line that guides EMF is characterized in terms of distributed
parameters or analyzed in terms of small sections with lumped (discrete)
parameters/components.
1. Understanding EM field (EMF) is essential to characterize and
understand electrical systems over a wide frequency.

2. Transmission line is physical structure that guide EMF

3. Knowledge of transmission line is important to understand signal

propagation (voltage and current waves or EMF) and signal integrity
 Wire type transmission lines

Two wire

One wire with ground plane

Coaxial cable
Printed circuit board (PCB) structures

Stripline (inner planes)

Microstrip
(outer planes)

Lands on PCB
(without inner planes)
 Two conductor transmission line

Electric field about a transmission Magnetic field about a

line caused by the voltage between transmission line caused by the
the two conductors current on the conductors

Equivalent circuit Assumption:

Lossless line

Representation of a transmission line as a distributed parameter circuit consisting

of cells (z) of per-unit-length inductance l and per-unit-length capacitance c.
 Transmission line theory
• Consider a short section of transmission line of length, z.
• A transmission line element is described in terms of R (/m), L (H/m), C
(F/m) and G (S/m) defined per unit length
• Consider a two wire transmission line

Distributed representation Lumped representation

R: conductor loss due to finite resistance of the conductors

L: total self inductance of two conductors
C: capacitance between two conductors due to close proximity
G: dielectric loss in the material between two conductors
R&L represent the loss in a transmission line
• KVL applied to transmission line circuit model gives,
(1)
• KCL gives,
(2)

• Dividing (1) and (2) by z and evaluating in the limit z0 we get,

Telegrapher’s equations

• For sinusoidal steady state condition we get differential equations,

coupled D.E. for V(z) and I(z) in transmission line.

• We get D.E. similar to wave equation for the current and voltage in
transmission line

where
complex propagation constant
• Solution to the travelling current and voltage wave is given by,

(3)
ez: forward travelling wave, ez: backward travelling wave
• From travelling wave current can be expressed
as,
(4)

• Characteristic impedance of the line, Zo is related to current and voltage

by,

• From Eqn. (3) & (4),

• Eqn. (4) can be rewritten as,
• In time domain,

where  is phase of Vo

• Wavelength on the line is,
• Phase velocity,
Transmission line parameters for commonly used lines
 Lossless transmission line
• R=G=0. Thus, and
• Characteristic impedance of the line, is a real number
• Voltage and current on lossless transmission line is written as,

where wavelength is,

and phase velocity is,

(1) Transmission line terminated in an arbitrary load

: line propagation constant

Z0: line impedance
• At z=0,

• Solving we get

and ;

• Line impedance at any point is given by

(2) Junction of two lossless transmission lines

• Load line is infinitely long/doesn’t have reflection from its end

• Then, Voltage wave in both lines are given by,

• At z=0 (boundary condition),

• Transmission coefficient between two points in a circuit is given by

insertion loss,
(3) Terminated lossless transmission line
• Let V0e-jz be incident wave generated
by a source at z<0
• Since ZLZ0, reflected wave will exist
• At z=0,
• Solving for V0- and substituting for V0- / V0+ gives, voltage reflection
coefficient:

• Total current and voltage on the line is given by,

Standing waves

• Time average power flow:

• Return loss of a line,

• When =0, ZL=Z0 (Matched load & no standing waves) and RL is  dB

• When ||=1, RL is 0 dB

• Magnitude of voltage on the line,

• Magnitude oscillates with position by

• Maximum occurs when and

• Minimum occurs when and

• As  es, Vmax/Vmin es i.e., oscillation increases

• Standing wave ratio (VSWR) of the line; real number [1, ]

• At any point along the line,

where (0) is (z=0).

• Input impedance of line at any z=-l,

• Case A: Short circuit termination (lossless line)
 ZL=0, = 1 and standing waves are given by,

 At z=0, V=0 and I=Imax and Zin at any point along the line,
• Case A: Short circuit termination (lossless line)
• Case B: Open circuit termination (lossless line)
 ZL=, = 1 and standing waves are given by,

 At z=0, I=0 and V=Vmax and Zin at any point along the line,
• Case B: Open circuit termination (lossless line)
 Time domain solution
• Graphical method for sketching waveform of terminal voltages
of a transmission line versus time
• Assuming lossless line
• Transmission line equations (sum of forward and backward
travelling wave) are given by

• Characteristic impedance of transmission line,

• Propagation velocity of a line,
• ,  depends on medium surrounding conductors of the line
• Current of each wave is related to the voltage wave by

• Let line length be L and let it be terminated by a load RL

• At z=L, load reflection coefficient is given by,

• I and V are expressed in terms of L,

Transmission line – Equivalent circuit before the wave reflected
at the load (z=L) arrives

(a)

Input voltage to a line Line fed by a source

(b)

Equivalent circuit Voltage fed to the line

TD = L/v, time delay to reach load at z=L.
For 0<t<2TD , no backward travelling wave occurs; V and I have only forward travelling waves
• Therefore,

• Forward travelling current and voltage waves launched in line are,

• The launched wave with amplitude, M=ZC/(RS+ZC) travels toward load at z=L
at t=TD

• At load, wave is reflected depending on load R L i.e., ML

• At t=2TD, reflected wave reaches source (z=0).

• Voltage reflection coefficient at source,

• A forward travelling wave, MLS is launched on line again

• At t=3TD, it reaches load. A wave of MLSL is sent back to source

 Wave reflection at a termination

(a) Wave launched on line

(b) Wave reflected at load

(c) Forward and reflected waves

(d) Forward and reflected waves

Bounce diagram
 Assignment-1
• At t=0, 30V battery with zeros resistance is connected to a
lossless line of length, L=400 m, wave velocity 200 m/s and
characteristics impedance, 50 . The line is terminated with
100  load.

• Sketch voltage wave on line at (a) t=1 s, (b) t=2.5 s, (c) t=4.5
s, (d) t=6.5 s
• Sketch current wave on line.
 Effect of pulse width: Ex. 1
• Consider a line of length, L=0.2 m, wave velocity 2x108 m/s
and characteristics impedance, 100 . The source voltage is a
pulse of 20 V amplitude and 1 ns duration. The source
resistance is 300  and load is open circuit.
– Sketch voltage wave at (a) input to the line and (b) load.
 Effect of pulse width: Ex. 1
Sketch voltage wave at (a) input to the line and (b) load.
(a)voltage wave at input to the line
(a)voltage wave at input to the load
 Effect of pulse width: Ex. 2
• Consider a line shown in Figure.

• Let source voltage be,

• Sketch voltage wave at (a) input to the line and (b) load.
 High-Speed Digital Interconnects and Signal Integrity

• At source (z=0),

• At load (z=L)

• Sum of source voltage waveforms scaled and delayed by

multiples of one time delay, TD.
• If load is matched to line impedance i.e., L=0

• Input and load voltages are same except for the time delay.

• Thus, line length does not matters.

 Effect of Terminations on Line Waveforms

• Input of CMOS gate is capacitive (5-15 pF) i.e., impedance 

• Output of CMOS gate 10-30 

• Consider two CMOS gates connected by a transmission line.

• Let output impedance of CMOS gate be 10 , Zc = 50 . S = -2/3, L = 1.

 Equivalent representation

• Assume a step input of 5V is output by Gate 1. Sketch the waveform at the

load
S = , L = +
Ringing causes logic
errors
 Effect of Terminations on Line Waveforms
• Sign of SL determines ringing
 Effect of Capacitive Terminations

• Let Rs=Zc, load be capacitive and Vs(t)=V0u(t); u(t):step input

• Laplace transform yields, ZL = 1/sC, s = 0 (Rs=Zc ) and

• Time constant, Tc = CZc (RC)

• As s = 0, there is only one forward travelling wave incident

at ZL and reflected wave travelling back to source
• Laplace transform for zero initial condition gives
Capacitive load introduces additional time delay, td in 50%
voltage point i.e., 0.5 V0

Initially short circuit then transitions to open circuit, td = 0.693Tc

 Effect of Inductive Terminations
• Let Rs=Zc, load be inductive and Vs(t)=V0u(t)
• Laplace transform yields, ZL = sL, s = 0 and
• Time constant, TL = L/Zc
• As s = 0, there is only one forward travelling wave incident at ZL
and reflected wave travelling back to source

• Laplace transform for zero initial condition gives

Initially open circuit then transitions to short

 Matching Schemes for Signal Integrity
• Mismatches at load and source can drastically differ from
what was sent
• Mismatches affect signal integrity
• CMOS gates have low output resistance and high input
impedance
• Series matching
Series resistance is added to gate output such that Rs+R=Zc
• Series matching – As RL is open circuit, no current flows
through line. Thus, series resistor R does not dissipate power.
• Parallel matching – Place resistor R in parallel with load

• Limitations of parallel matching

• VL<Vs and no reflections to boost
• Even for open circuit load, line will
draw current when Vs is in high state
• Hence, R will consume power
 Effects of Line Discontinuities
• Line cross section determines line impedance in PCB
• Line cross section changes/discontinuities  line impedance
change  Reflections
Wave incident from left:

w1 w2

Wave incident from right:

Line discontinuity
 Line discontinuities
Wave incident from left Wave incident from right
Let and Let
where where

Voltage at junction, Voltage at junction,

. .
Hence, Hence,
. .
Therefore, Therefore,
. .
 Ex. 3
• Sketch voltage wave at AA’ and BB’
 When Does the Line Not Matter
• Matching takes care of bounces

• Matching is not needed for very short line

• Electrically short i.e., L< 1/10(v/fmax)

• The spectral content of a digital signal is given by, BW=1/r

• Highest significant frequency, fmax=1/ r

• If delay introduced by the line, r >10 TD

• For very short line lengths, mismatches should not significantly

degrade output waveform
Example of when line length matters
For r >10 TD impedance mismatches and
line length doesn’t matter
Self reading (included in portion)
4.2 THE PER-UNIT-LENGTH PARAMETERS
• Different transmission lines,
• line impedance equations, and
• per unit-length parameters
 Effects of feeding multiple lines

Problems that influence time delay and lead to signal integrity issues
1. Effect of terminations
2. Line length
3. Transitions in line
4. Clock skew
5. Feeding/distribution of lines

Example of clock skew

Unequal delay Equal delay

• Series distribution

Gate 1 Gate 2
• Parallel distribution

Gate 1

Gate 2
 Series distribution

• Series matching, Rs+R=Zc is possible

• Parallel matching at junction with R+Rs=Zc for open circuit

loads
• 1st line input impedance, Zc/2 (R=Zc ; R|| Zc of second line)

• Multiple reflections occur

Parallel distribution
• Source sees two lines in parallel
• Therefore,
• At load, RL is open. Therefore, full reflection
occurs and it reaches source
• At source it sees impedance of Rs||Zc

Series matching such that Rs=Zc

Refl. & trans. coeffs are -1/3 and 2/3

Parallel matching such that R=Zc

across loads. Draws more current
and current supplied by driver circuit
increases with number of loads