Module 1

Introduction
 Outline
 A Brief History
 MOS Transistors
 CMOS Logic

CMOS VLSI Design 4th Ed.

 A Brief History
 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
 2010 Courtesy Texas Instruments

– Intel Core i7 processor

• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
[Trinh09]
© 2009 IEEE.

CMOS VLSI Design 4th Ed.

 Growth Rate
 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller,cheaper, faster, lower in power!
– Revolutionary effects on society

[Moore65]
Electronics Magazine

CMOS VLSI Design 4th Ed.

 Annual Sales
 >1019 transistors manufactured in 2008
– 1 billion for every human on the planet

CMOS VLSI Design 4th Ed.

 Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs

CMOS VLSI Design 4th Ed.

 Ten years later, Jack Kilby at Texas Instruments
realized the potential for miniaturization if multiple
transistors could be built on one piece of silicon.
 Bell Labs developed the bipolar junction transistor.
Bipolar transistors were more reliable, less noisy,
and more power-efficient. Early integrated circuits
primarily used bipolar transistors.
 By the 1960s, Metal Oxide Semiconductor Field
Effect Transistors (MOSFETs) began to enter
production.

CMOS VLSI Design 4th Ed.

 Continued…
 They come in two flavors: nMOS and pMOS, using
n-type and p-type silicon, respectively.
 In 1963, Frank Wanlass at Fairchild described the
first logic gates using MOSFETs .
 Fairchild’s gates used both nMOS and pMOS
transistors, earning the name Complementary Metal
Oxide Semiconductor, or CMOS.

CMOS VLSI Design 4th Ed.

 Transistor Types
 Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

CMOS VLSI Design 4th Ed.

 MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

 1980s-present: CMOS processes for low idle power
CMOS VLSI Design 4th Ed.
 Moore’s Law: Then
 In 1965, Gordon Moore observed that plotting the
number of transistors that can be most economically
manufactured on a chip gives a straight line on a
semilogarithmic scale .
 At the time, he found transistor count doubling every
18 months. This observation has been called
Moore’s Law.

CMOS VLSI Design 4th Ed.

 Moore’s Law: Then
 The number of transistors in Intel microprocessors
has doubled every 26 months since the invention of
the 4004.

Integration Levels
SSI: 10 gates -
Inverter
MSI: 1000 gates
LSI: 10,000 gates
[Moore65]
Electronics Magazine
VLSI: > 10k gates
CMOS VLSI Design 4th Ed.
 Integration Levels
 SSI: 10 gates –Ex.Inverter
 MSI: 1000 gates-Ex.Counter
 LSI: 10,000 gates-Ex.8 bit Microprocessor
 VLSI: > 10k gates –Most of the integrated circuits

CMOS VLSI Design 4th Ed.

And Now…

CMOS VLSI Design 4th Ed.

 Feature Size
 Minimum feature size shrinking 30% every 2-3 years

CMOS VLSI Design 4th Ed.

 Corollaries
 Many other factors grow exponentially
– Ex: clock frequency, processor performance

CMOS VLSI Design 4th Ed.

 CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

CMOS VLSI Design 4th Ed.

 Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

CMOS VLSI Design 4th Ed.

 Series and Parallel
 nMOS: 1 = ON g1
a
0
a
0
a
1
a
1
a

 pMOS: 0 = ON
g2
b
0
b
1
b
0
b
1
b


(a) OFF OFF OFF ON

Series: both must be ON a a a a a

 Parallel: either can be ON g1

g2
0 0 1 1

0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

CMOS VLSI Design 4th Ed.

 Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

CMOS VLSI Design 4th Ed.

 Compound Gates
 Compound gates can do any inverting function
 Ex:
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

CMOS VLSI Design 4th Ed.

 Example: O3AI


A
B
C D
Y
D
A B C

CMOS VLSI Design 4th Ed.

 Signal Strength
 Strength of signal
– How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
– But degraded or weak 1
 pMOS pass strong 1
– But degraded or weak 0
 Thus nMOS are best for pull-down network

CMOS VLSI Design 4th Ed.

 Pass Transistors
 Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1

CMOS VLSI Design 4th Ed.

 Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

CMOS VLSI Design 4th Ed.

 Tristates
 Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y

EN

CMOS VLSI Design 4th Ed.

 Nonrestoring Tristate
 Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN
CMOS VLSI Design 4th Ed.
 Tristate Inverter
 Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

CMOS VLSI Design 4th Ed.

 Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

CMOS VLSI Design 4th Ed.

 Gate-Level Mux Design
 Y SD1  SD0 (too many transistors)
 How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

CMOS VLSI Design 4th Ed.

 Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
– Only 4 transistors
S

D0
S Y
D1

CMOS VLSI Design 4th Ed.

 Inverting Mux
 Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

CMOS VLSI Design 4th Ed.

 4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

CMOS VLSI Design 4th Ed.

 D Latch
 When CLK = 1, latch is transparent
– D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
– Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

CMOS VLSI Design 4th Ed.

 D Latch Design
 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

CMOS VLSI Design 4th Ed.

 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

CMOS VLSI Design 4th Ed.

 D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

CLK
CLK
D
Flop

D Q
Q

CMOS VLSI Design 4th Ed.

 D Flip-flop Design
 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

CMOS VLSI Design 4th Ed.

D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

CMOS VLSI Design 4th Ed.

 Race Condition
 Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late
– Sees first flip-flop change and captures its result
– Called hold-time failure or race condition

CLK1
CLK1 CLK2 CLK2

Q1 Q1
Flop

Flop

D Q2
Q2

CMOS VLSI Design 4th Ed.

 Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
– Industry manages skew more carefully instead
2 1
QM
D Q

2 2 1 1

2 1

1

2

CMOS VLSI Design 4th Ed.

 Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

CMOS VLSI Design 4th Ed.

Example: Inverter

CMOS VLSI Design 4th Ed.

 Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 

CMOS VLSI Design 4th Ed.

 Stick Diagrams
 Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

CMOS VLSI Design 4th Ed.

 Wiring Tracks
 A wiring track is the space required for a wire
– 4  width, 4  spacing from neighbor = 8  pitch
 Transistors also consume one wiring track

CMOS VLSI Design 4th Ed.

 Well spacing
 Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

CMOS VLSI Design 4th Ed.

 Area Estimation
 Estimate area by counting wiring tracks
– Multiply by 8 to express in 

40 

32 

CMOS VLSI Design 4th Ed.

 Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
–
Y  A  B  C D
VDD
A B C D

6 tracks =
48 
Y

GND
5 tracks =
40 

CMOS VLSI Design 4th Ed.