Sequential VHDL

Dr. Hakem Beitollahi

Computer Engineering Department

Elmo Sanat University
Outline
 Concurrent and Sequential Statements
 Process statement
 Wait statement
 Signals & variables in process
 Global variables (Shared)
 Postponed Process
 If statements
 Case statements
 Loop statements
 Clk generation
 Flip-Flops
 Synchron and Asynchron reset
2
Concurrent and Sequential Statements
 VHDL provides two different types of execution:
sequential and concurrent

 Different types of execution are useful for

modeling of real hardware

 Sequential statements view hardware from a

programmer approach

 Concurrent statements are order-independent

and asynchronous

3
Concurrent and Sequential Statements
 Concurrent type such as: when-else, with-select, signal
assignment, and etc.

 Sequential type such as: if-then-else, case statement,

loop statements, variable assignment, inside process and
etc.,

 Both sequential and concurrent such as: signal

assignment, constants, function and procedure calls,
after delay, and etc.

 Important: codes inside process, function and

procedures are sequential.

 Important: codes inside architecture are concurrent

4
Process statement (I)
 The process in VHDL is the mechanism by which
sequential statements can be executed in the
correct sequence.
 Several processes execute concurrently
 Processes in an architecture are executed
concurrently with all other concurrent
statements.
 Execution is controlled either via sensitivity list
(contains trigger signals), or wait-statements
 The statements inside the process is executed
whenever one or more elements of the sensitive
list change value.

5
Process statement (II)
 Process statements are executed
concurrently but the statements inside a
process are executed sequentially.
 Every process is executed once upon
initialization
 A process statement has a declaration
section and a statement part.
 In the declaration section, types, variables,
constants, subprograms, and so on can be
declared.
 The statement part contains only sequential
statements.

6
Process Definition

VARIABLES are optional. If used, they must be declared in the

declarative part
of the PROCESS
The initial value is not synthesizable, being only taken into
consideration in simulations.

The use of a label is also optional. Its purpose is to improve code

readability

7
Process

JustToShow: process JustToShow: process

Begin Begin
Some statement 1; Some statement 1;
Some statement 2;
Some statement 2; Some statement 3;
Some statement 3; Some statement 4;
Some statement 4; wait<condition>;
Some statement 5; end process JustToShow;
end process JustToShow;

8
 Process
JustToShow: process ( )
JustToShow: process Begin
Begin
Some statement 1;
Some statement 1;
Some statement 2; Some statement 2;
Some statement 3; Some statement 3;
Some statement 4; Some statement 4;
wait on SomeSig end process JustToShow;
end process JustToShow;

 VHDL provides a construct called sensitivity list of a process

 The list specified next to the process keyword.
 The same as wait on sensitivity_list at the end of a process

9
 Process
Sensitive list

JustToShow: process (signa1,signal2,signal3)

Begin
Some statement 1;
Some statement 2;
Some statement 3; Signal2 has changed
Signal3 has changed
Some statement 4;
Some statement 5;
end process JustToShow;

10
 Process: an example
ARCHITECTURE archlist OF list IS
BEGIN
nand_test: PROCESS (a,b) the process ‘nand’ is
BEGIN the process ‘nand’ is
sensitive to signals ‘a’ and
c <= NOT (a AND b); sensitive to signals ‘a’ and
END PROCESS nand_test; ‘b’
‘b’i.e.,
i.e.,whenever
wheneversignal
signal
END archlist; ‘a’
‘a’or
or‘b’
‘b’changes
changesvalue,
value,
the
thestatements
statementsinside
insideof
ofthe
the
c process
processwill
willbe
beevaluated
evaluated

11
Wait statement
 A process may be suspended upon execution of a wait statement in
the process. The process remains suspended until its reactivation
condition is met

 Three kind of reactivation condition can be specified in a wait

statement

timeout wait for time-expression; //simulation only

condition wait until condition; //Synthesizable
signal sensitivity wait on signal-list; //Synthesizable

 Conditions can be mixed. e.g

wait on A, B until Enable = 1;

 It is illegal to use wait statement in a process with a sensitivity list

12
Wait Until
 WAIT UNTIL signal_condition;
 The WAIT UNTIL statement accepts only one
signal
 More appropriate for synchronous code than
asynchronous
 WAIT UNTIL must be the first statement in the
PROCESS
 The PROCESS will be executed every time
the condition is met.

13
Wait Until (Example)
PROCESS -- no sensitivity list
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
IF (rst='1') THEN
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
output <= input;
END IF;
END PROCESS;

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WAIT ON
 WAIT ON signal1 [, signal2, ... ];
 WAIT ON accepts multiple signals
 The PROCESS is put on hold until any of the
signals listed changes
PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
output <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
output <= input;
END IF;
END PROCESS;

15
Wait: an Example
Or_process : process
Or_process : process (In1,
In2) Begin
begin wait on In1, In2;
Output <= In1 or In2; Output <= In1 or
In2;
end process;
end process;

• Wait for type expression Wait for 10ns (simulation)

• Wait until condition Wait until CLK=‘1’
• Wait on sensitivity list Wait on Enable
• Complex wait Wait unit date after 10ns (simulation)

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Variables versus signals in process

17
Variables vs. signals in process
 Variables and signals show a
fundamentally different behavior.

 In a process, the last signal assignment to

a signal is carried out when the process
execution is suspended.

 Value assignments to variables, however,

are carried out immediately.
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 Signals and Processes
 Goal: the difference between how a signal
assignment and variable assignment behave in
the process statement.
...
signal x,y,z : bit; If the signal y changes then an event will be
... scheduled on x to make it the same as y.
process (y)
begin An event is scheduled on z to make it the
x<=y; opposite of x.
z<=not x;
end process; Question: will the value of z be the
opposite of y?
The answer is NO, because when the
second statement is executed, the event
on x has not been processed yet, and the
event scheduled on z will be the opposite
of the value of x
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 Variables and Processes
process (y)
variable x,z : bit; The value of the variable z would be the
begin opposite of the value of y because the
x:=y; value of the variable x is changed
z:=not x; immediately.
end process;

Variables are only available within

•

processes:
• Name within process declarations
• Known only in this process Possible assignments:

Signal to variable
Variable to signal
Types have to match

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Variables in process
architecture RTL of XYZ is
signal A, B, C : integer range 0 to 7;
signal Y, Z : integer range 0 to 15;
begin
process (A, B, C)
variable M, N : integer range 0 to 7;
begin
M := A;
N := B;
Z <= M + N;
M := C;
Y <= M + N;
end process;
end RTL;

21
 Variables vs. signals in process
signal A,B,C:
signal A,B,C: integer;
integer; signal Y, Z :
signal Y, Z : integer;
integer; signal M, N :
integer;
begin begin
process (A,B,C) process
variable M, N: (A,B,C,M,N)
integer;
begin
begin
M := A; M <= A;

N := B; N <= B;

Z <= M + N; Z <= M + N;

M := C; 22 M <= C;
Variables vs. signals in process (II)
 Signal values are assigned after the
process execution
 Only the last signal assignment is carried
out
 M ⇐ A; is overwritten by M ⇐ C;
 The 2nd adder input is connected to C

23
Exam question (Check Yourself)
 What is the value of sum in the following two pieces of
code? Please determine the value of sum for the first 4
clocks
entity mysig is entity myvar is
port(clk: in bit; port(clk: in bit;
sum: out integer range 0 to 256); sum: out integer range 0 to 256);
end mysig; end myvar;
architecture beh of mysig is architecture beh of myvar is
signal sig1: integer :=1; begin
signal sig2: integer :=2; process(clk)
signal sig3: integer :=3; variable var1: integer :=1;
begin variable var2: integer :=2;
process(clk) variable var3: integer :=3;
begin begin
if(clk'event and clk='1') then if(clk'event and clk='1') then
sig1 <=sig2 + sig3; var1:=var2 + var3;
sig2 <= sig1; var2 := var1;
sig3 <=sig2; var3 :=var2;
sum<=sig1 + sig2 + sig3; sum<=var1 + var2 + var3;
end if; end if;
end process; end process;
end architecture; end architecture;
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Exam Question: Solution I
In myvar program:
In clock 1:
Var1 = 2+3 = 5
Var2 = 5
Var3 = 5  sum = 5 + 5 + 5  sum = 15
In clock 2:
Var1 = 5 + 5 = 10
Var2 = 10
Var3 = 10  sum = 10 + 10 + 10  sum =30;
In clock3:
Var1 = 10 + 10 = 20
Var2 = 20
Var3 = 20  sum 20 + 20 + 20  sum = 60
In clock4:
Var1 = 20 + 20 = 40
Var2 = 40
Var3 = 40  sum = 40 + 40 + 40  sum = 120 25
 Exam Question: Solution II
In clock3:
In mysig program:
Now, the signal assignments of clock 2 are taken here;
In clock1:
while the signal assignments of clock 3 are taken at the
All signal assignments are taken at the beginning of beginning of clock 4. So, we have
clock 2; thereby in clock 1 you have
Sig1 = 1 + 2 = 3
Sig1 = 1
Sig2 = 5 (the value of signal sig1 of clock 2)
Sig2 = 2
Sig3 = 1 (the value of sig2 of clock 2)  sum = 3 + 5
Sig3 = 3  sum = 1+2+3  sum = 6 + 1  sum = 9
In clock2: In clock4:
Now, the signal assignments of clock 1 are taken here; Now, the signal assignments of clock 3 are taken here;
while the signal assignments of clock 2 are taken at the while the signal assignments of clock 4 are taken at the
beginning of clock 3. So, we have beginning of clock 5. So, we have
Sig1 = 2 + 3 = 5
Sig2 = 1 (the value of signal sig1 of clock 1) Sig1 = 5 + 1 = 6
Sig3 = 2 (the value of sig2 of clock 1)  sum = 5 + 1 Sig2 = 3 (the value of signal sig1 of clock 3)
+2=8
Sig3 = 5 (the value of sig2 of clock 3)  sum = 6 + 3
+ 5  sum = 14

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Global variables (Shared)

27
Global variables
 In VHDL 93, global variables are allowed.

 These variables are not only visible within a process but within the entire architecture.

 The problem may occur, that two processes assign a different value to a global variable at
the same time. It is not clear then, which of these processes assigns the value to the
variable last.
 This can lead to a non-deterministic behavior!

 In synthesizable VHDL code global variables must not be used.

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 Global variables (II)
• Accessible by all processes of an
architecture (shared variables)
architecture BEHAVE of SHARED is
shared variable S : integer;
begin
• Can introduce non-determinism
process (A, B)
begin
S := A + B;
end process;

process (A, B)
begin
S := A - B;
end process;
end BEHAVE;

Not to be used in synthesizable code

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Postponed Process

30
Postponed Process (I)

Activates 3 Times
Ex:Process (a, b, c) Once Per Sensitivity
List Signal Change
Begin
......
End Process;

 IF a, b, c Change in Zero-Time but with one -Delay from one another 

 Multiple Process Activation (within -Delay of Each other)
 The final Activation Signal Transactions will Dominate
 Unnecessary Execution of Processes result in Slower Operation
 Postponed Processes Activate Only After All Sensitivity List Signals
Stabilize. 31
 Postponed Process (II)
Activates Only After
All Sensitivity List
Signals Stabilize (c
in this case).

Ex: Postponed Process (a, b, c)

Begin
......
End Process;

 Concurrent Statements, e.g. Signal Assignment, Are

Also Sensitive to Changes in Signals on Their Right
Hand Side  Postponed Keyword Can Be Used in
This Case As Well.

Example

Concurrent1: Postponed a <= b AND c OR d ;

32
If Statement

33
If Statement
 The general form is
if condition1 then
statement1
elsif condition2 then
statement2
else
statement3
end if;

34
 If Example: Two-input NAND gate
The process declaration section
Declares a VHDL package that provides the declares a local variable named
necessary information with 9 state logic. temp.

The architecture contains only one

ARCHITECTURE mynand OF mynand2 IS
statement, a concurrent process BEGIN
statement. PROCESS( a, b )
VARIABLE temp : std_logic;
LIBRARY IEEE;
BEGIN
USE explicit sensitivity lis
temp := NOT (a and b);
IEEE.std_logic_1164.ALL;
IF (temp = '1') THEN
c <= temp AFTER 6 ns;
ENTITY mynand2 is
ELSIF (temp = '0') THEN
PORT( a, b : IN std_logic;
c <= temp AFTER 5 ns;
c : OUT std_logic);
ELSE
END entity;
The process statement part has c <= temp AFTER 6 ns;
two sequential statements in it END IF;
END PROCESS;
END architecture;
35
 If: an Example
The name of the architecture is the same name as the
entity name. This is legal

library ieee; architecture myand of myand is

use ieee.std_logic_1164.all; constant Delay: time:= 5 ns;
begin
entity myand is And_process : process (in1, in2)
begin
port(in1, in2: in std_logic; if In1 = '0' or In2 = '0' then
out1: out std_logic); Out1 <= '0' after Delay;
end entity; elsif In1 = 'X' or In2 = 'X' then
Out1 <= 'X' after Delay;
else
Logical or for checking a Out1 <= '1' after Delay;
condition. It is not a end if;
gate!
In an if statement, using end process;
parenthesis is optional end architecture;

36
 If: an Example
process
begin
if (reset = ‘1’) then
A <= ‘0’ ;
elsif (clk’event and clk = ‘1’) then
A <= ‘B’;
end if;
wait on reset, clk;
end process;
process (clk,reset)
begin
if (reset = ‘1’) then
A <= ‘0’;
elsif (clk’event and clk = ‘1’) then
A <= ‘B’;
end if;
end process;
37
If: an Example

IF (x<y) THEN temp:="11111111";

ELSIF (x=y AND w='0') THEN
temp:="11110000";
ELSE temp:=(OTHERS =>'0');
End if;

38
 One-digit Counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY counter IS
PORT (clk : IN STD_LOGIC;
digit : OUT INTEGER RANGE 0 TO 9);
END counter;
---------------------------------------------
ARCHITECTURE counter OF counter IS
BEGIN
count: PROCESS(clk)
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
IF (clk'EVENT AND clk='1') THEN
temp := temp + 1;
IF (temp=10) THEN temp := 0;
END IF;
END IF;
digit <= temp;
END PROCESS count;
END counter;

39
Case Statements

40
Case statement
 Syntax
case expression is
when choice 1 =>
statement_A;
when choice 3 to 5 =>
statement_B;
when choice 8 downto 6 =>
statement_C;
when choice 9 | 13 | 17 =>
statement_D;
when others =>
statement_E;
end case;

41
Case statement: an Example
 MUX (41)
mycase_pro: process (s, c, d, e, f)
begin
case s is
when "00" =>
pout <= c; C
when "01" =>
pout <= d; D POUT
when "10" => E
pout <= e;
when others => F
pout <= f; S
end case;
end process mycase_pro;

42
Case statement
 CASE allows multiple assignments for
each test condition
WHEN value -- single value
WHEN value1 To value2 -- range, for enumerated data types
only
WHEN value1 | value2 |... -- value1 or value2 or ...

43
Null
 Nothing to do
 Equivalent to No Operation
 It can be used by case statement
process (count)
begin
case count is
when 0 =>
dout <= “00”;
when 1 to 15 =>
dout <= “01”;
when 16 to 255 =>
dout <= “10”;
when others =>
null;
end case;
end process;

44
Loops

45
Loop (I)
 The LOOP statement is used whenever an
operation needs to be repeated.
 The LOOP statement has an optional
label, which can be used to identify the
LOOP statement.
 VHDL provides three kinds of Loop statements
 Simple loop

 for loop

 while loop

46
Simple Loop
 Simple loop
 Simple loop encloses a set of statements in a
structure which is set to loop forever
 The general form is
label1 : loop
statements
end loop label1;

47
Simple loop: Example
library ieee;
use ieee.std_logic_1164.all;
entity WhileTest is
port(A: in integer range 0 to 31;
Z: out std_logic_vector(3 downto 0));
end entity;
Note VHDL allows maximum 10000 iterations.
architecture test of WhileTest is
begin
process (A)
variable I : integer range 0 to 4;
begin
Z <= "0000";
I := 0;
L1: loop
exit L1 when I = 4;
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
end process;

48
For loop (I)
 The FOR loop loops as many times as specified in the
discrete_range, unless the loop is exited
 The general form
loop_label: -- optional
for loop_variable in range loop
statements
end loop loop_label;
 Example

49
 For Loop Example

architecture LoopTest of LoopTest

library ieee; is
use ieee.std_logic_1164.all; signal t: integer;
use ieee.numeric_std.all; begin
entity LoopTest is t<= to_integer(unsigned(A));
port(A: in std_logic_vector(1 downto 0); process(A)
Z: out std_logic_vector(3 downto 0)); begin
end entity; Z<="0000";
for i in 0 to 3 loop
if i=t then
Package for converting std_logic to integer Z(i)<='1';
end if;
end loop;
end process;
end architecture;

50
For loop (II)
 In some languages, the loop index (in this
example, i) can be assigned a value inside
the loop to change its value.
 VHDL does not allow any assignment to the
loop index.
 The index value i is locally declared by the
FOR statement.

The variable i does not need to be declared
explicitly in the process, function, or procedure
 If another variable of the same name exists in
the process, then these two variables are
treated as separate variables

51
 For loop (III)

PROCESS(i)
BEGIN
x <= i + 1; -- x is a signal
FOR i IN 1 to a/2 LOOP
q(i) := a; -- q is a variable
END LOOP;
END PROCESS;

 The index value i is not the same object as the signal i that was
used to calculate the new value for signal x.
 Inside the FOR loop, when a reference is made to i, the local index is
retrieved.
 But outside the FOR loop, when a reference is made to i, the value of the
signal i in the sensitivity list of the process is retrieved.
52
For loop (IV)
 The values used to specify the range in the
FOR loop need not be specific integer
values.
 The range can be any discrete range.
 See Examples

53
 For loop (V)

PROCESS(clk)
TYPE day_of_week IS (sun, mon, tue, wed, thur, fri, sat);
BEGIN
FOR i IN day_of_week LOOP  The range is specified by the type.
IF i = sat THEN
son <= mow_lawn;  Here, the compiler determines that
ELSIF i = sun THEN the leftmost value is sun, and the
church <= family; rightmost value is sat.
ELSE
dad <= go_to_work;  The range then is determined as from
END IF;
END LOOP; sun to sat.
END PROCESS;

54
For loop (VI)
 If an ascending range is desired, use the
to clause. The downto clause can be
used to create a descending range.
 See Example

PROCESS(x, y)
BEGIN
FOR i IN x downto y LOOP
q(i) := w(i);
END LOOP;
END PROCESS;

55
While Loop

56
While loop (I)
 The WHILE condition LOOP statement loops as long as
the condition expression is TRUE.
 The general form:
loop_label:
while condition loop
statements
end loop loop_label;
 See Example

57
 While loop (II)
library ieee; architecture test of WhileTest is
use ieee.std_logic_1164.all; begin
process (A)
entity WhileTest is variable I :
port(A: in integer range 0 to 3; integer range 0 to 4;
Z: out std_logic_vector(3 downto 0)); begin
end entity; Z <= "0000";
I := 0;
while (I <= 3) loop
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
end process;
end architecture;

58
Exit and Next statement
 Exit statement is a sequential statement closely
associated with loops and causes the loop to be exited
for i in 0 to 7 loop
if ( i = 4 ) then
exit;
end if;
end loop;
 Next statement is used to advance control to the next iteration of the
loop
for i in 0 to 7 loop
if ( i = 4 ) then
next;
end if;
end loop;

59
Nested loop
process
begin
for i in 0 to 3 loop
for j in 0 to 3 loop
wait for 10 ns;
b <= b + 1;
end loop;
a <= a + 1;
end loop;
wait;
end process;

60
Generate positive Edge of Clock

61
 CLK Generation
 The most popular clk generation

Process (clk) Process (clk) Process (clk)

Begin Begin Begin
if( clk’event and clk=‘1’) then if( clk=‘1’) then wait until clk=‘1’;
…. …. ….
Selection
Selection depends on
end if; end if; depends on end process;
synthesis
synthesis tools
end process; end process; tools
Process (clk)
Begin
if( clk’event and clk=‘1’ and clk’last_value=‘0’) then
….
end if;
end process;
62
D-Flip Flop
library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (data, clk : in std_logic;
q : out std_logic);
end d_ff;

architecture behav of d_ff is

begin
process (clk) begin
if (clk'event and clk = '1') then
q <= data;
end if;
end process;
end behav;

63
D-Flip Flop with asynchron reset
library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (data, clk,reset : in std_logic;
q : out std_logic);
end d_ff;

architecture behav of d_ff is

begin
process (clk, reset) begin
if reset=‘1’ then
q<=‘0’;
elsif (clk'event and clk = '1') then reset
q <= data;
end if;
end process;
end behav;

64
D-Flip Flop with synchron reset
library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (data, clk,reset : in std_logic;
q : out std_logic);
end d_ff;

architecture behav of d_ff is

begin
process (clk, reset) begin
if( clk’event and clk=‘1’) then
if reset=‘1’ then
q<=‘0’; reset
elsif
q <= data;
end if;
end if;
end process;
end behav;

65
Using Sequential Code to Design
Combinational Circuits

66
Using Sequential Code to Design Combinational
Circuits

 Sequential code can be used to implement

either sequential or combinational circuits.
 To design a combinational circuit, the
following rules should be observed
 Rule 1: Make sure that all input signals used
(read) in the PROCESS appear in its
sensitivity list.
 Rule 2: Make sure that all combinations of the
input/output signals are included in the code;

67
 Example

ARCHITECTURE example OF example IS

BEGIN
PROCESS (a, b, c, d, sel)
ENTITY example IS BEGIN
PORT (a, b, c, d: IN STD_LOGIC; IF (sel=0) THEN
sel: IN INTEGER RANGE 0 TO 3; x<=a;
y<='0';
x, y: OUT STD_LOGIC); ELSIF (sel=1) THEN
END example; x<=b;
y<='1';
ELSIF (sel=2) THEN
x<=c;
ELSE
x<=d;
END IF;
END PROCESS;
END example; 68