Data Types

Dr. Hakem Beitollahi

Computer Engineering Department

Elmo Sanat University
Outline
 Data Types

—2
Data Types

3
 Data Types (I)
Types

Access Composite
(equivalent to pointers in C)
allows dynamic memory allocation
Scalar Array Record

Integer Real Boolean Character Bit Std_logic Enumerated Physical

4
Data Types (II)

—5
Data Types (III)

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Data Types (II)
 Scalar Types
 Integer Type

Minimum range for any implementation as defined by standard: -2,147,483,648 to
2,147,483,647
 Natural type (subtype of integer)

Minimum range for any implementation as defined by standard: 0 to 2,147,483,647
 Positive type (subtype of integer)

Minimum range for any implementation as defined by standard: 1 to 2,147,483,647
 Real Type [Simulation only]

Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38
 Boolean Type

It has two values of “True” and “False”
 Character type [Simulation only]

It supports all characters such as ‘a’..’z’, ‘[‘, ‘{‘ and etc.
 Bit type

It has two values of ‘1’ and ‘0’
 Std_ulogic type:

It is IEEE standard

contain: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘w’, ‘L’, ‘H’, ‘-’
 Std_logic type (subtype of std_ulogic)

It is IEEE standard

contain: ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘w’, ‘L’, ‘H’, ‘-’

7
STD_LOGIC
 STD_LOGIC is defined in the library
std_logic_1164.This is a nine valued logic system.

It has 9 values: 'U', 'X', '0', '1', 'Z', 'W', 'L' ,'H' and '-'.
The meaning of each of these characters are:


U = uninitialized [Simulation only]
X = unknown - a multisource line is driven '0' and '1'
simultaneously [synthesizable]
0 = logic 0 [synthesizable]
1 = logic 1 [synthesizable]
Z = high impedance (tri state) [synthesizable]
W = weak unknown [Simulation only]
L = weak ‘0’[Simulation only]
H = weak ‘1’[Simulation only]
- = don't care [Simulation only]

8
 Data Types (IV)
 Some examples
 x0 <= '0'; -- bit or std_logic gets '0‘
 x1 <= "00011111"; -- bit_vector, std_logic_vector, signed, or unsigned
 x2 <= "0001_1111"; -- underscore allowed to ease visualization
(work only for std_logic)
 x3 <= "101111" -- binary representation of decimal 47
 x4 <= B"101111" -- binary representation of decimal 47
 x6 <= X"2F" -- hexadecimal representation of decimal 47
 n <= 1200; -- integer
 m <= 1_200; -- integer, underscore allowed
 IF ready THEN... -- Boolean, executed if ready=TRUE
 y <= 1.2E-5; -- real, not synthesizable

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Data Types (V)
 Example: Legal and illegal operations between
data of different types
SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
...
a <= b(5); -- legal (same scalar type: BIT)
b(0) <= a; -- legal (same scalar type: BIT)
c <= d(5); -- legal (same scalar type: STD_LOGIC)
d(0) <= c; -- legal (same scalar type: STD_LOGIC)
a <= c; -- illegal (type mismatch: BIT x STD_LOGIC)
b <= d; -- illegal (type mismatch: BIT_VECTOR x STD_LOGIC_VECTOR)
e <= b; -- illegal (type mismatch: INTEGER x BIT_VECTOR)
e <= d; -- illegal (type mismatch: INTEGER x STD_LOGIC_VECTOR)
c<=a; -- illegal (type mismatch: between c and a
— 10
Std_ulogic vs. std_logic (I)
 The two types std_logic and std_ulogic
both have in common that they can
represent the following values:
‘1’ Logic 1
‘0’ Logic 0
‘Z’ High impedance
‘W’ Weak signal, can’t tell if 0 or 1
‘L’ Weak 0, pulldown
‘H’ Weak 1, pullup
‘-‘ Don’t care
‘U’ Uninitialized
‘X’ Unknown, multiple drivers

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Std_ulogic vs. std_logic (II)
 Std_ulogic is the unresolved type

if multiple drivers are driving different values onto a signal of the
std_ulogic type, that’s not going to work.

Conflicting drivers is an error in VHDL.

The simulation won’t compile, or the design won’t synthesize.
architecture sim of UnresolvedTb is
signal Sig1 : std_ulogic := '0';
begin

-- Driver A
Sig1 <= '0';

-- Driver B
Sig1 <= '1' after 20 ns;

end architecture;

if we try to compile this in ModeSim, it reports the following error:

** Error: C:/proj/tb.vhd(8): Nonresolved signal 'Sig1' has multiple sources.
 Note that bit and bit_vector are also unresolved
— 12
Std_ulogic vs. std_logic (III)
 std_logic – The resolved type
 The std_logic can represent the same values as the
std_ulogic, but it’s a resolved type.
 SUBTYPE std_logic IS resolved std_ulogic;

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Std_ulogic vs. std_logic (IV)
 Repeat the same example
architecture sim of UnresolvedTb is
signal Sig1 : std_logic := '0';
begin

-- Driver A
Sig1 <= '0';

-- Driver B
Sig1 <= '1' after 20 ns;

end architecture;

 The code now compiles in ModelSim without errors.

When we run it, it produces this waveform:

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 Data Types (III)
 Scalar Types (cntd.)
 Enumerated Types [synthesizable]

A type whose values are defined by listing (enumerating) them
explicitly.

Mostly state machines use it

Example:
Type state_type is (start, idle, waiting, run)
Signal state: state_type;
 Physical Types: [Simulation only]

A numeric type for representing some physical quantity, such as
mass, length, time or voltage.
TYPE resistence IS RANGE 0 to 1000000
UNITS
ohm; -- ohm
Kohm = 1000 ohm; -- 1 K
Mohm = 1000 kohm; -- 1 M
END UNITS;
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 Data Types (IV)
 Physical type (cntd.) [Simulation only]
 Time units are the only predefined physical type
in VHDL
TYPE TIME IS RANGE -2147483647 to 2147483647
UNITS
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
END UNITS;

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User-Defined Data Types
 VHDL also allows the user to define
his/her own data types
 TYPE my_integer IS RANGE -32 TO 32;
-- A user-defined subset of integers.
 TYPE student_grade IS RANGE 0 TO 100;

-- A user-defined subset of integers or naturals.

 Enumerated Types


TYPE color IS (red, green, blue, white);
-- Another enumerated data type.

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Data Types (VIII)
 Subtype
 A type with a constraints
 Assignments that are out of the subtype range result in an error
 Main reason for using a subtype rather than specifying a new
type

Though operations between data of different types are not allowed,
they are allowed between a subtype and its corresponding base type
 Assignment from subtype to base type and vice versa is possible and ok.
 Example

Subtype my_int is integer range 0 to 3215;

subtype byte1 is std_logic_vector(7 downto 0);

SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';
-- Recall that STD_LOGIC=('X','0','1','Z','W','L','H','-').
-- Therefore, my_logic=('0','1','Z').

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Data type (An example)
 Which one is legal and which one is illegal
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';
SIGNAL a: BIT;
SIGNAL b: STD_LOGIC;
SIGNAL c: my_logic;
...
b <= a; --illegal (type mismatch: BIT versus STD_LOGIC)
b <= c; --legal (same "base" type: STD_LOGIC)

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Subtype (An example)
 See the code
architecture Behavioral of example is
Subtype A1 is integer range -8 to 8;
Subtype B1 is integer range -16 to 16;
subtype C1 is B1 range -4 to 4;
signal x:integer;
signal y: A1;
signal z:B1;
signal w:C1;

begin
x<=y; --Ok and no error
y<=x; --OK and no error
y<=z; --OK and no error
z<=w; --OK and no error
y<=w; --OK and no error
end Behavioral;

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Downto vs. to in VHDL
 If you take a processor, for Little endian
systems we can use "downto" and for
Bigendian systems we use "to".

signal t1 : std_logic_vector(7 downto 0); --
7th bit is MSB and 0th bit is LSB here.

and,

signal t2 : std_logic_vector(0 to 7); --0th
bit is MSB and 7th bit is LSB here.

You are free to use both types of
representations, just have to make sure that
other parts of the design are written accordingly.
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Data Types (Array I)
 Composite Types
 Array Types:

Used to collect one or more elements of a similar
type in a single construct

Elements can be any VHDL data type

They can be one-dimensional (1D), two-
dimensional (2D), or one-dimensional-by-one-
dimensional (1Dx1D).

Other dimensions are possible, but NOT
synthesizable

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 Data Types (Array II)

(a): scalar (single bit)

(b) 1D also called vector
(c) 1Dx1D
(d) 2D

Predefined Scalars: BIT, STD_LOGIC, and BOOLEAN [synthesizable]

Predefined Vectors: BIT_VECTOR, STD_LOGIC_VECTOR, INTEGER, SIGNED, and

UNSIGNED [synthesizable]
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Data Types (Array III)
 There are no pre-defined 2D or 1Dx1D arrays
 must be specified by the user
 To do so, the new TYPE must first be defined
 The new SIGNAL, VARIABLE, or CONSTANT
can be declared using that data type
TYPE type_name IS ARRAY (specification) OF data_type;
 To make use of the new array type:
SIGNAL signal_name: type_name [:= initial_value];

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Data Types (Array IV)
 Example: 1Dx1D array
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array
TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array
SIGNAL x: matrix; -- 1Dx1D signal

 Alternative way
TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO
0);

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Data Types (Array V)
 Example: 2D array
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
-- 2D array

0
1
2
3
7 6 5 4 3 2 1 0

 Example: Array initialization

... :="0001"; -- for 1D array
... :=('0','0','0','1') -- for 1D array
... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or -- 2D array — 26
 Data Types (Array VI)
 Multi-dimensional array (more)
 Example:

Type data4x8 is array (0 to 3) of std_logic_vector(7 downto 0);

Type data3x4x8 is array (0 to 2) of data4x8;

Type truth_table is array(0 to 7, 0 to 4) Of BIT;

Access of array elements by an example

Architecture rtl of ex is
Signal a_vect : std_logic_vector (4 downto 0)
Begin
A_vect(4)<=‘1’;
A_vect(3 downto 0)<=“0110”;
End rtl;

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Data Types (Array VII)-Example
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array
TYPE array1 IS ARRAY (0 TO 3) OF row; -- 1Dx1D array
TYPE array2 IS ARRAY (3 downto 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); --
1Dx1D
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array
SIGNAL x: row;
SIGNAL y: array1;
SIGNAL v: array2;
SIGNAL w: array3;
Types of scalar assignments- all of them are legal

x(0) <= y(1)(2); -- notice two pairs of parenthesis -- (y is 1Dx1D)

x(1) <= v(2)(3); -- two pairs of parenthesis (v is 1Dx1D)
x(2) <= w(2,1); -- a single pair of parenthesis (w is 2D)
y(1)(1) <= x(6);
y(2)(0) <= v(0)(0);
y(0)(0) <= w(3,3);
w(1,1) <= x(7);
w(3,0) <= v(0)(3);

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 Data Types (Array VII)-Example
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array
TYPE array1 IS ARRAY (0 TO 3) OF row; -- 1Dx1D array
TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); -- 1Dx1D
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array
SIGNAL x: row;
SIGNAL y: array1;
SIGNAL v: array2;
SIGNAL w: array3;
Vector assignments
x <= y(0); -- legal (same data types: ROW)
x <= v(1); -- illegal (type mismatch: ROW x --STD_LOGIC_VECTOR)
x <= w(2); -- illegal (w must have 2D index)
x <= w(2, 2 DOWNTO 0); -- illegal (type mismatch: ROW x -- STD_LOGIC)

v(0) <= w(2, 2 DOWNTO 0); -- illegal (mismatch: STD_LOGIC_VECTOR -- x STD_LOGIC)

v(0) <= w(2); -- illegal (w must have 2D index)
y(1) <= v(3); -- illegal (type mismatch: ROW x -- STD_LOGIC_VECTOR)
y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); -- legal (same type, -- same size)
v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); -- legal (same type, -- same size)
w(1, 5 DOWNTO 1) <= v(2)(4 DOWNTO 0); -- illegal (type mismatch)

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 Data Types (VII)
 Composite Types (contd.)
 Record type

Used to collect one or more elements of a different types in single construct

Elements can be any VHDL data type

Elements are accessed through field name

Architecture beh of ex is
Type data is record
Year: integer range 1996 to 2099;
Month: integer range 1 to 12;
val: std_logic_vector(7 downto 0);
Check: Bit;
End record;
Signal d: data;
Begin
d.year<=2008;
d.month<=4;
d.val<=“01110111”
d.check<=‘1’;
End; 30
Data Type (Signed and Unsigned)
 These types are defined in the std_logic_arith package of
the ieee library.
 SIGNAL x: SIGNED (7 DOWNTO 0);
 SIGNAL y: UNSIGNED (0 TO 3);
 Notice that their syntax is similar to that of
STD_LOGIC_VECTOR
 An UNSIGNED value is a number never lower than zero
 If type SIGNED is used instead, the value can be positive or
negative
 SIGNED and UNSIGNED data types are intended mainly
for arithmetic operations (similar to integer signals)
 Unlike std_logic_vector, logical operations are not
allowed
— 31
 Data Type (Signed and Unsigned)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; -- extra package necessary
...
SIGNAL a: SIGNED (7 DOWNTO 0);
SIGNAL b: SIGNED (7 DOWNTO 0);
SIGNAL x: SIGNED (7 DOWNTO 0);
...
v <= a + b; -- legal (arithmetic operation OK)
w <= a AND b; -- illegal (logical operation not OK)

LIBRARY ieee;
USE ieee.std_logic_1164.all; -- no extra package required
...
SIGNAL a: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b; -- illegal (arithmetic operation not OK)
w <= a AND b; -- legal (logical operation OK)
— 32
Data types
 There is a simple way of allowing data of type
STD_LOGIC_VECTOR to participate directly in
arithmetic operations
 Using packages std_logic_signed or
std_logic_unsigned
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; -- extra package included
...
SIGNAL a: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b; -- legal (arithmetic operation OK), unsigned
w <= a AND b; -- legal (logical operation OK)
— 33
Data Conversion

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Data Conversion (I)
 VHDL does not allow direct operations (arithmetic,
logical, etc.) between data of different types.
 It is often necessary to convert data from one type to
another.
 If the data are closely related, then the std_logic_1164 of
the ieee library provides straightforward conversion
functions
TYPE long IS INTEGER RANGE -100 TO 100;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
...
y <= 2*x + 5; -- error, type mismatch
y <= long(2*x + 5); -- OK, result converted into type long

— 35
Data Conversion (II)
 Conversion using predefined functions
 Data conversion functions can be found in the
std_logic_arith package
 conv_integer(p) : Converts a parameter p of type INTEGER,
UNSIGNED or SIGNED to an INTEGER value.

Notice that STD_LOGIC_VECTOR is not included.
 conv_unsigned(p, b): Converts a parameter p of type INTEGER,
UNSIGNED or SIGNED, to an UNSIGNED value with size b bits.
 conv_signed(p, b): Converts a parameter p of type INTEGER,
UNSIGNED or SIGNED to a SIGNED value with size b bits.
 conv_std_logic_vector(p, b): Converts a parameter p of type
INTEGER, UNSIGNED,or SIGNED to a STD_LOGIC_VECTOR
value with size b bits.

— 36
Data Conversion (III)
Example
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
-- Legal operation: a+b is converted from UNSIGNED to an
-- 8-bit STD_LOGIC_VECTOR value, then assigned to y.

— 37
 Check Yourself
 Consider the following data types: a <= x(2);
b <= x(2);
TYPE array1 IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; b <= y(3,5);
TYPE array2 IS ARRAY (3 DOWNTO 0, 7 DOWNTO 0) OF STD_LOGIC;b <= w(5)(3);
TYPE array3 IS ARRAY (3 DOWNTO 0) OF array1; y(1)(0) <= z(7);
x(0) <= y(0,0);
SIGNAL a : BIT; x <= "11100000";
SIGNAL b : STD_LOGIC;: a <= "0000000";
SIGNAL x : array1; y(1) <= x;
SIGNAL y : array2; w(0) <= y;
SIGNAL w : array3; w(1) <= (7=>'1', OTHERS=>'0');
SIGNAL z : STD_LOGIC_VECTOR (7 DOWNTO 0); w(2)(7 DOWNTO 0) <= x;
w(0)(7 DOWNTO 6) <= z(5
DOWNTO 4);
x(3) <= x(5 DOWNTO 5);
Which statement of the red-rectangle is illegal and which is correct y <= ((OTHERS=>'0'),
(OTHERS=>'0'),
(OTHERS=>'0'), "10000001");
z(6) <= x(5);
z(6 DOWNTO 4) <= x(5 DOWNTO
3);
z(6 DOWNTO 4) <= y(5 DOWNTO
3);
y(0, 7 DOWNTO 0) <= z;
w(2,2) <= '1';

— 38
Answer of check yourself
a <= x(2); -- Error Type of a1 is incompatible with type of x
b <= x(2);
b <= y(3,5);
b <= w(5)(3); -- Error 5 is not included in the index range, 3 downto 0, of array w.
y(1)(0) <= z(7); -- Error Wrong index type for y.
x(0) <= y(0,0);
x <= "11100000";
a <= "0000000"; --Error Type of a1 is incompatible with type of 0000000.
y(1) <= x; --Error Wrong index type for y.
w(0) <= y; -- Error Type of w is incompatible with type of y.
w(1) <= (7=>'1', OTHERS=>'0');
w(2)(7 DOWNTO 0) <= x;
w(0)(7 DOWNTO 6) <= z(5 DOWNTO 4); --Error Type of w is incompatible with type of z.
x(3) <= x(5 DOWNTO 5); --Error Type of x is incompatible with type of x.
y <= ((OTHERS=>'0'), (OTHERS=>'0'),
(OTHERS=>'0'), "10000001");
z(6) <= x(5);
z(6 DOWNTO 4) <= x(5 DOWNTO 3); --Error Type of z is incompatible with type of x.
z(6 DOWNTO 4) <= y(5 DOWNTO 3); --Error Wrong slice type for y.
y(0, 7 DOWNTO 0) <= z; --Error parse error, unexpected DOWNTO, expecting COMMA or CLOSEPAR
w(2,2) <= '1'; --Error Wrong index type for w.

— 39