Concurrent Statements

(Behavioral)
VHDL

Dr. Hakem Beitollahi

Computer Engineering Department

Elmo Sanat University
Outline
 Intro to Concurrent statements
 Delay Types
 When-else instruction
 With-select-when instruction
 Generics
 Constants
 VHDL Objects

—2
Introduction to Behavioral Modeling
 The signal assignment statement

a <= b;

read as follows: a gets the value of b.

The current value of signal b is assigned to signal a.

This statement is executed whenever signal b
changes value.
 Introduce a nonzero delay value for the
assignment

a <= b after 10 ns;

Read as follows: a gets the value of b when 10
nanoseconds of time have elapsed.
 Both of the preceding statements are concurrent
signal assignment statements.
Example: A simple AND gate
ENTITY and2 IS
PORT ( a, b : IN BIT;
PORT ( c : OUT BIT );
END and2;

ARCHITECTURE and2_behav OF and2

IS
BEGIN
c <= a AND b AFTER 5 ns;
END and2_behav;
 The value of signal c may be assigned a new value after 5
nanoseconds whenever either a or b changes value.
 The entity design unit describes the ports of the and2 gate.
 There are two inputs a and b, as well as one output c.

 The architecture and2_behave for entity and2 contains one concurrent

signal assignment statement
Delay Types

5
Delay Types (I)
 Delay is created by scheduling a signal
assignment for a future time
 Just for simulation (Not Synthesizable)
 There are three main types of delay
supported by VHDL
 Inertial delay
 Transport delay
 Delta delay
Input Delay Output

6
 Delay Types (II)
 Inertial Delay
 It absorbs pulses and wavelets of shorter
duration than the specified delay
Output <= inertial not Input after 10 ns;

The Inertial delay is the default delay and

the reserved word inertial can be
omitted. Input Delay Output

Output

Input

5 10 15 20 25 30 35
10 ns
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Delay Types (III)
 Transport Delay
 Must be explicitly specified by user
 Passes all input transitions with delay

-- TRANSPORT must be specified

Output <= transport not Input after 10 ns;

Input Delay Output

Output
Input

5 10 15 20 25 30 35

10 ns 10 ns 8
Delta Delay (IV)
 Default signal assignment propagation delay if no
delay is explicitly prescribed
 VHDL signal assignments do not take place immediately

 E.g.
Input Dealy Output

Output <= NOT Input;

-- Output assumes new value in one delta cycle

Output
Input

5 10 15 20 25 30 35
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Check Yourself
 Draw a waveform for the following signal assignment. For
each requested statement, please determine the time.
 X <= Y after 5 ns;
 X <= transport Y after 5 ns;
 X<=Y;

— 10
 Inerial Delay vs. Transport delay

The transport delay is used to model the delay introduced by wire connection

The inertial delay models the delay introduced by an analog port, which means,
it is analogous to the delay in devices that respond only if the signal value
persists on their inputs for a given amount of time.

 It is useful in order to ignore input glitches whose duration is less than the
port delay.
— 11
Concurrent Statements

12
 Concurrent Statements (I)

Three types of concurrent statements

used in dataflow descriptions

Boolean Equations with-select-when when-else

For concurrent For selective For conditional

signal assignments signal assignments signal assignments

Concurrent Conditional statements

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 Concurrent Statements (II)
 When – Else : (Conditional concurrent signal
assignment)
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

Value N
…
Value N-1
Target Signal
Value 2
Value 1
Condition N-1

Condition 2
Condition 1

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 Concurrent Statements (III)
 When-else Example: MUX
Entity mux is
Port(I0, I1, I2, I3 : in bit;
A, B : in bit;
F : out bit);
End mux;
Architecture mux_arch of mux is
Signal S: bit_vector(1 downto 0); We do not talk
Begin about logic gate,
S<= A & B; and or nand ect, we
F <= I0 when (s = "00") else are describing the
behavior of circuit
I1 when (s = "01") else using a high level
I2 when (s = "10") else description.
I3;
end mux_arch; 15
 Unaffected signals
 Value of the signal is not changed
 VHDL 1993 only! library IEEE;
use IEEE.std_logic_1164.all;

 The keyword unaffected indicates a entity pr_encoder is

choice where the signal is not given a port (S0, S1,S2,S3: in std_logic;
new assignment. Z : out std_logic_vector (1 downto 0));
 This is roughly equivalent to the use of end entity pr_encoder;
the null statement
architecture behavioral of pr_encoder is
begin
Z <= “00” after 5 ns when S0 = ‘1’ else
“01” after 5 ns when S1 = ‘1’ else
unaffected when S2 = ‘1’ else
“11” after 5 ns when S3 = ‘1’ else
“00” after 5 ns;
end architecture behavioral;
— 16
Check yourself
 Using When-else statement, implement
the following circuit

— 17
 Concurrent Statements (IV)
 With –Select-When : (selected concurrent signal
assignment)
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

expression1 choices_1
expression2 choices_2
target_signal

expressionN choices_N

choice expression
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 Concurrent Statements (V)
 With-select-when Example: MUX
Entity mux is
Port(I0, I1, I2, I3 : in bit;
A, B : in bit;
F : out bit);
End mux;
Architecture mux_arch of mux is
Signal S: bit_vector(1 downto 0);
Begin We do not talk
S<= A & B; about logic gate,
With S select and or nand ect, we
F<= I0 when “00“, are describing the
I1 when "01“, behavior of circuit
using a high level
I2 when “10“,
description.
I3 when “11”;
end mux_arch;
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Check yourself
 Using With-select-when statement,
implement an active-high 2-4 decoder

— 20
 Concurrent Statements (Boolean equations)

 Example: MUX
Entity mux is
Port(I0, I1, I2, I3 : in bit;
A, B : in bit;
F : out bit);
End
Architecture mux_arch of mux is
Begin
F<= ( not A and not B and I0) or
( not A and B and II) or
( A and not B and I2) or
( A and B and I3)
end mux_arch;
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Generics and Constants

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 Generics
 If the model has a parameter, then it is defined using generics.
generics
 Generics are a means of passing specific information into an entity. They
do not have a mode (direction):

generic ( Please note the way of assignment

gain : integer := 4;
time_delay : time := 10 ns );

entity entity_name is
generic (generic list);
port (port list);
end entity_name;

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Example
Define a parameterize value
entity AN2_GENERIC is
generic (DELAY: time := 10 ns);
port (A,B : in bit;
Z : out bit);
end AN2_GENERIC;

architecture BEH of AN2_GENERIC is Using the generic parameter

begin
Z <= A and B after DELAY;
end Beh;

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More about Generics
 Generics are basically useful when you make
multiple instances of a component.

You can have different value of generic for each
instance.
 Example

Instantiate a simple AND gate that has a generic
declared for its Propagation Delay

You can have different value of propagation delay for
each instance.

If the value of generic is not specified in instance then
its default value is used which you can specify in the
entity of this AND gate.

More examples, when the structural model
(components) is taught.

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 Constants
 It is also possible to include model specific
constants in the entity using the standard
declaration of constants method
constant constant_name : type_name := constant_value;
constant delay1 : time := 5 ns;
 Improve the readability of the code
 Allow for easy updating
 Constants can be declared in any declarative
region, and can be used within that region.
 Their value cannot be changed once
declared.

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 Example

entity AN2_GENERIC is
entity AN2_GENERIC is
port (A,B : in bit;
port (A,B : in bit;
Z : out bit);
Z : out bit);
end AN2_GENERIC;
constant delay: time:= 10 ns;
end AN2_GENERIC;
architecture BEH of AN2_GENERIC is
constant delay: time:= 10 ns;
architecture BEH of AN2_GENERIC is
begin
begin
Z <= A and B after delay;
Z <= A and B after delay;
end Beh;
end Beh;

See location of definition

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VHDL Objects
 There are three types of objects in VHDL
 Constants
 Signals
 Variables
 VHDL is strongly depends on types
 You cannot assign a value to a different type

You should use “type conversion”

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VHDL Objects (Signals I)
 Signals are used for communication
between components
 Signals can be seen as real and physical
wires
 Signal assignment

Signal_name <= value
 Signals can be declared in

Package declaration

Architecture

Block

Subprograms (Functions and Procedures)

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 VHDL Objects (Signals II)
 Signals must be declared outside a process
 Declaration form
signal list_of_signal_names : type_name
[ := initial value ];

• Declared in an architecture can be used

anywhere within that architecture
VHDL Objects (Variables I)
 Variables are used only in processes and
subprograms (functions and procedures)
 All variable assignments take place
immediately
 Variables can be assigned by the assignment
operator ":=".
 Example:

variable var1: bit_vector (7 downto 0);
var1 := "01010011";
 Variable is used when you want to create a
serialized code, unlike the normal parallel
code.

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 VHDL Objects (Variables II)
 What are they for:
Local storage in processes, procedures, and
functions
 Declaring variables
variable list_of_variable_names : type_name
[ := initial value ];

• Variables must be declared within the process in

which they are used and are local to the process
• Also in subprograms and can be used only inside them
 Variables vs. Signals
 Variable assignment statement
variable_name := expression;
– expression is evaluated and the variable is
instantaneously updated
(no delay, not even delta delay)
• Signal assignment statement
signal_name <= expression [after delay];
– expression is evaluated and the signal is scheduled to
change after delay; if no delay is specified the signal is
scheduled to be updated after a delta delay
 Signals versus Variables
 A key difference between signals and variables is the assignment
delay
ARCHITECTURE signals of test is ARCHITECTURE variables of test is
SIGNAL a, b, c, out_1, out_2 : BIT; SIGNAL a, b, c: BIT;
BEGIN BEGIN
PROCESS (clk,a, b, c) PROCESS (clk,a, b, c)
BEGIN VARIABLE out_3, out_4 : BIT;
if(clk’event and clk=‘1’) then BEGIN
out_1 <= a NAND b; if(clk’event and clk=‘1’) then
out_2 <= out_1 XOR c; out_3 := a NAND b;
end if; out_4 := out_3 XOR c;
END PROCESS; end if;
END signals; END PROCESS;
END variables;

CLK a b c out_1 out_2 CLK a b c out_3 out_4

0 0 1 1 x x
1 1 1 1 1 0 0 0 1 1 1 0
1+d 1 1 1 0 1 1 1 1 1 0 1

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Signals vs. variables
 variables:
 They are local;
 no delay;
 declared within process

 signals:
 They are global (before begin);
 delay due to wire;
 declared before keyword begin

— 35
Objects scope
 VHDL limits the visibility of the objects,
depending on where they are declared
 The scope of the object is as follows
 Objects declared in a package are global to all entities
that use that package
 Objects declared in an entity are global to all
architectures that use that entity
 Objects declared in an architecture are available
to all statements in that architecture
 Objects declared in a process are available to
only that process
 Scoping rules apply to constants, variables, and
signals
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