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Zeroth Review

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Immanuel Stephen
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14 views7 pages

Zeroth Review

Uploaded by

Immanuel Stephen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Cryptographic Accelerator on FPGA

Vishal. B – 21011102021
Pushkala. S – 21011102075
Emmanuel.S.M – 21011102031
G.S. Ruparani - 21011102032
Ms. Dhivya Stephen
Shiv Nadar University Chennai
Problem Statement

Embedded systems, such as those in IoT devices, automotive units, and smart devices, face significant
challenges when performing computationally heavy cryptographic operations like AES. These systems
operate under strict constraints in terms of power consumption, processing speed, and memory.
Cryptographic tasks, essential for securing data, demand considerable computational power, especially for
real-time encryption and decryption. However, low-power microcontrollers often lack the capacity to handle
these operations efficiently, leading to bottlenecks in performance and delays in data processing.

This inefficiency results in critical issues like increased power consumption, which is detrimental to battery-
operated devices, reducing their operational lifespan. Slower encryption also introduces latency, making
systems vulnerable to security breaches. In safety-critical applications, such as automotive or industrial
control, compromised encryption can have severe real-world consequences. Thus, optimizing cryptographic
operations is essential to maintain both security and performance in resource-constrained environments.
Proposed Solution
FPGA-Based Cryptographic Accelerator: An FPGA-based cryptographic accelerator processes
cryptographic operations like AES directly in hardware, leveraging the FPGA's parallel processing
capabilities. This setup allows for faster execution of computationally demanding algorithms compared to
software implementations on general-purpose processors. By using dedicated hardware logic for encryption
and decryption, the FPGA improves both speed and energy efficiency, making it ideal for resource-
constrained environments.
Co-Processor Interface (CPI): The Co-Processor Interface (CPI) facilitates seamless
communication between the embedded processor and the FPGA, enabling efficient task delegation. Through
this interface, the embedded processor offloads cryptographic tasks to the FPGA, allowing it to focus on less
intensive system control and communication functions. The CPI minimizes delays and overhead, ensuring
low-latency interaction and maintaining overall system performance.
Offloading Cryptographic Workload: Offloading cryptographic tasks to the FPGA allows the
embedded processor to manage system-level functions without the burden of heavy computational
workloads. This division enhances overall system performance, as the FPGA handles high-throughput
cryptographic operations efficiently. Consequently, the embedded processor benefits from reduced power
consumption and heat generation, resulting in improved responsiveness and longevity for devices operating
in power-constrained environments.
Existing Solutions

1. Hardware-Based Cryptographic Accelerators


a. FPGA-Based Cryptographic Accelerators
b. Microcontroller-Based Cryptographic Hardware
2. Software-Based Cryptographic Libraries
3. Hybrid Technologies (SoCs with Integrated FPGA/Accelerators)
Current Work
1. FPGA Development Board (Selection)
2. Embedded System (Microcontroller or SoC)
3. Communication Interface (CPI Implementation)
Architecture

Memory Map Co-Processor Interface (CPI)


References
https://drive.google.com/drive/folders/1bVHnKVlYOL41pJSeq9EIrYCB1C_2yT6F?usp=sharing

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