Chapter 4.

Input/Output
Organization
Computer Architecture and
Organization

1
Overview
Computer has ability to exchange data with other devices.

This exchange includes:

 Human-computer communication
 Computer-computer communication
 Computer-device communication
 …

2
Overview
Computer has Processor, Memory, Buses for communication
and the I/O devices connected to it.

The I/P devices include: The O/P devices include:

Keyboard Monitor
Scanner Printer
Mouse Speaker
Microphone Plotter
Camera Projectors
Joystick Headphones
Light pen. Optical mark readers
Barcode Reader. DVD or CD-ROM
Touchscreen Sound card
3
Video card
Accessing I/O Devices
Computer Buses
 Internal Buses
 External Buses (External device
Connections)

4
Single Bus Structure

Processor Memory

Bus

I/O device 1 I/O device n

Figure 4.1. A single-bus structure.

The interconnection network consists of circuits needed to transfer information

between the processor, the memory unit, and a number of I/O devices. 5
Types of I/O Accesses

 Memory Mapped I/O

 Program Controlled I/O

6
Memory-Mapped I/O
 When I/O devices and the memory share the same address space, the arrangement
is called memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer data to or from

an I/O device.
Move DATAIN, R0
Move R0, DATAOUT
 The regular instruction fetch cycle phases processes the instruction.

 Accessing memory locations are implemented using bit-storage circuits (flip-flops)

organized as I/O registers within processor

I/O -Mapped I/O

 They cannot be accessed like any other memory location.
 Separate address and data buses are required for memory and I/O devices
 Some processors use direct special In and Out instructions to perform I/O transfer.
 They are used to perform Input and Output and only AC register can

7
Program-Controlled I/O
Processor executes a program that gives it direct control of the I/O operation, for
sensing device status, sending a read or write command, and transferring the data.

The overall operation of the programmed I/O can be summaries as follow:

 The processor executes the program when finds an instruction related to I/O.
 Processor issues command to appropriate I/O module.
 The I/O module performs the requested action based on the processor command
(READ/WRITE) and set the appropriate bits in the I/O status register.
 The processor will periodically check the status of the I/O module until it find that the
operation is complete.

 I/O devices operate at speeds that are very much different from that of the processor.
 Keyboard, for example, is very slow.

8
Interface
The mode of transferring information between internal storage and
external I/O devices is known as I/O interface or input/output
interface.

9
Interface
 An I/O device is connected to the interconnection network by
using a circuit, called the device interface.

 The device interface provides the means for data transfer, by the
exchange of status and control information needed to facilitate the data
transfers and govern the operation of the device.
 The Processor can recognize the Device using Address Decoders.
 The Interface has registers that can be accessed by the processor, to
 Serve as a buffer for data transfers
 Hold information about the current status of the device, and
 Store the information that controls the operational behavior of the
device (Control signals)
 The data, Status, and control registers are accessed by the program
instructions as if they were memory locations.
10
Three Major Mechanisms
 Polling
the device- by the processor-
Program-controlled I/O
 Interrupt

 Direct Memory Access (DMA)

11
Interrupts

12
Overview
 In program-controlled I/O, the program enters a wait loop in which
it repeatedly tests the device status. During the period, the
processor is not performing any useful computation.
 However, in many situations other tasks can be performed while
waiting for an I/O device to become ready.
 Let the device alert the processor.

13
Interrupt

14
Types of Interrupts

15
Types of Interrupts
 Maskable Interrupts
 Non-Maskable Interrupts
 Hardware Interrupts : Generated through external devices (Low Priority)
 Software Interrupts : Generated through the internal OS (High Priority)

16
Vectored Interrupt & Non- Vectored
Interrupt

17
Interrupt Processing

18
Overview of Interrupt Processing
 Steps
 Step 1: Stops the current instruction execution.
 Step 2: Stores the address of current instruction in temporary location.
 Step 3: Control Starts processing the interrupt occurred.
 Step 4: Restores the current Instruction execution after completion of processing
interrupt.

19
Overview

 In program-controlled I/O, the program enters

a wait loop in which it repeatedly tests the
device status. During the period, the processor
is not performing any useful computation.
 However, in many situations other tasks can be
performed while waiting for an I/O device to
become ready.
 Let the device alert the processor.

An interrupt service routine (ISR) is a piece of

code that runs in response to an interrupt signal
from a hardware device or software event.
20
21
 Since the interrupt request can come at any
Enabling andtheDisabling
time, it may alter sequence of events from
that envisaged by the programmer.
Interrupts
 Interrupts must be controlled.

22
Basic Concept: I/O in KB and Display
device (Program controlled I/O Using Polling)

 Shown are registers involved in data

transfer operation.

 Status registers has 2 control flags

SIN & SOUT.

 KIRQ & DIRQ are 2 control flags in

status registers for KB and Display.

 The DEN & KEN bits are used in

Control registers.

 Data from KB is stored in DATAIN

and Data to Display is stored in
DATAOUT.

23
Program controlled I/O

 Processor repeatedly checks the status flag (SIN / SOUT) to achieve synchronization
between the Processor and I/O device.
 This is known as Processor Polls the device.
 Other methods:
 Interrupt – I/O device sends special signal request to processor
 DMA-used for high-speed I/O devices, the device interface transfers the data
directly to and from the memory without continuous involvement of the
24
processor.
I/O in KB and Display devices

25
I/O in KB and Display devices

26
Interrupt Priority

27
Interrupt Priority

28
Interrupt Hardware

29
Interrupt Hardware

30
Interrupt Hardware
When all device switches are OPEN, the voltage in the interrupt-request line =Vdd

Resistor R- is known as Pull-up resistor, as it pulls up the line voltage state when
the switches are open

NOT Gate Interrupt request line MOS

(Metal-
Oxide-
Several I/O devices Semiconduc
I/O devices switch tor) circuit is
employed in
interrupt line
applications
due to its
ability to
detect
changes in
logic levels.

31
Interrupt Hardware: Working

33
ENABLING AND DISABLING
INTERRUPTS

34
ENABLING AND DISABLING
INTERRUPTS

 The interrupt request signal will be

active until it learns that the
Enabling
processor and Disabling
has responded to its
Interrupts
request. This must be handled to
avoid successive interruptions.
 Let the interrupt be disabled/enabled in the
interrupt-service routine.
 Let the processor automatically disable
interrupts before starting the execution of the
interrupt-service routine.
35
HANDLING MULTIPLE
DEVICES

36
Handling Multiple Devices
Given that different operationally independent devices are connected to
the Processor, there are many questions to be addressed.
How can the processor recognize the device requesting an interrupt?
Given that different devices are likely to require different interrupt-
service routines, how can the processor obtain the starting address of
the appropriate routine in each case?
 (Vectored interrupts)

Should a device be allowed to interrupt the processor while another

interrupt is being serviced?
 (Interrupt nesting)

How should two or more simultaneous interrupt requests be handled?

 (Daisy-chain)

37
 The interrupt request signal will be active
until it learns that the processor has
Enabling
responded to itsand Disabling
request. This must be
Interrupts
handled to avoid successive interruptions.
 Let the interrupt be disabled/enabled in the interrupt-
service routine.
 Let the processor automatically disable interrupts before
starting the execution of the interrupt-service routine.

38
Question 1
CONTEXT:
Different operationally independent devices are connected to the Processor

How can the processor recognize the device requesting an interrupt?

IRQ Bit
E.g. KIRQ Bit, DIRQ Bit

39
Drawback: Processor cycles and hence the time wasted in the Polling
40
process
Question 2

 Given that different devices are likely to require different

interrupt-service routines, how can the processor obtain
the starting address of the appropriate routine in each
case?
 (Vectored interrupts)

41
Vectored Interrupts
A device requesting an interrupt can identify
itself directly to the processor by sending
a special code to the processor over the
bus.
 Interrupt vector

 Avoid bus collision

42
Interrupt Nesting
 Simple solution: only accept one interrupt at a time, then disable
all others.
 Problem: some interrupts cannot be held too long.
 Priority structure

INTR 1 I NTR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration
circuit

Figure 4.7. Implementation of interrupt priority using individual

43
interrupt-request and acknowledge lines.
Simultaneous Requests I NTR

Processor
Device 1 Device 2 Device n
INTA

(a) Daisy chain

I NTR 1

Device Device
INTA1
Processor

INTR p

Device Device
INTA p
Priority arbitration
circuit

(b) Arrangement of priority groups

44

Figure 4.8. Interrupt priority schemes.

Controlling Device Requests
 Some I/O devices may not be allowed to
issue interrupt requests to the processor.
 At device end, an interrupt-enable bit in a
control register determines whether the
device is allowed to generate an interrupt
request.
 At processor end, either an interrupt enable
bit in the PS register or a priority structure
determines whether a given interrupt request
will be accepted.
45
Exceptions
 Recoveryfrom errors
 Debugging
 Trace
 Breakpoint
 Privilege exception

46
Use of Interrupts in Operating
Systems
 The OS and the application program pass
control back and forth using software
interrupts.
 Supervisor mode / user mode

 Multitasking (time-slicing)

 Process – running, runnable, blocked

 Program state

47
Processor Examples

48
 15 13 10 8 4 3 2 1 0

T S X N Z V C

Trace
Condition
Interrupt Codes
Supervisor
Priority

Figure 4.14. Processor status register in the 68000 processor.

49
 Mainprogram
MOVE.L #LINE,PNTR Initializebufferpointer.
CLR EOL Clearend-of-line indicator.
ORI.B #4,CONTROL Setbit KEN.
MOVE #$100,SR Setprocessorpriority to1.
..
.
In
terrupt-service
routine
READ MOVEM.L A0/D0,– (A7) SaveregistersA0,D0 onstack.
MOVEA.L PNTR,A0 Loadaddresspointer.
MOVE.B DATAIN,D0 Get input character.
MOVE.B D0,(A0)+ Store it inmemorybuffer.
MOVE.L A0,PNTR Updatepointer.
CMPI.B #$0D,D0 Check ifCarriageReturn.
BNE RTRN
MOVE #1,EOL Indicateend ofline.
ANDI.B #$FB,CONTROL Clearbit KEN.
RTRN MOVEM.L (A7)+,A0/D0 RestoreregistersD0, A0.
RTE

Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

50
Direct Memory Access

51
DMA
 Think about the overhead in both polling and
interrupting mechanisms when a large block of data
need to be transferred between the processor and
the I/O device.
 A special control unit may be provided to allow
transfer of a block of data directly between an
external device and the main memory, without
continuous intervention by the processor – direct
memory access (DMA).
 The DMA controller provides the memory address
and all the bus signals needed for data transfer,
increment the memory address for successive
words, and keep track of the number of transfers.
52
DMA Procedure
 Processor sends the starting address, the number of
data, and the direction of transfer to DMA controller.
 Processor suspends the application program
requesting DMA, starts DMA transfer, and starts
another program.
 After the DMA transfer is done, DMA controller
sends an interrupt signal to the processor.
 The processor puts the suspended program in the
Runnable state.

53
DMA Register
31 30 1 0

Status and control

IRQ Done
IE R/ W

Starting address

Word count

Figure 4.18. Registers in a DMA interface.

54
System
Main
Processor
memory

System bus

Disk/DMA DMA
controller controller Printer Keyboard

Disk Disk Network

Interface

Figure 4.19. Use of DMA controllers in a computer system. 55

Memory Access
 Memory access by the processor and the
DMA controller are interwoven.
 DMA device has higher priority.
 Among all DMA requests, top priority is given
to high-speed peripherals.
 Cycle stealing
 Block (burst) mode
 Data buffer
 Conflicts

56
Bus Arbitration
 The device that is allowed to initiate data
transfers on the bus at any given time is
called the bus master.
 Bus arbitration is the process by which the
next device to become the bus master is
selected and bus mastership is transferred to
it.
 Need to establish a priority system.
 Two approaches: centralized and distributed

57
Centralized Arbitration

B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2

Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.

58
Centralized Arbitration
Time

BR

BG1

BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Figure 4.21. Sequence of signals during transfer of b us mastership

for the devices in Figure 4.20.

59
Distributed Arbitration
Vcc

ARB 3
ARB 2
ARB 1
ARB 0
Start-Arbitration

O.C.

0 1 0 1 0 1 1 1

Interface circuit
for device A

Figure 4.22. A distributed arbitration scheme. 60

Buses

61
Overview
 The primary function of a bus is to provide a
communications path for the transfer of data.
 A bus protocol is the set of rules that govern the
behavior of various devices connected to the bus as
to when to place information on the bus, assert
control signals, etc.
 Three types of bus lines: data, address, control
 The bus control signals also carry timing
information.
 Bus master (initiator) / slave (target)
62
Synchronous Bus Timing
Time

Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle

Figure 4.23. Timing of an input transfer on a synchronous bus.

63
Synchronous Bus Detailed
Timing Time

Bus clock

Seen by master t AM
Address and
command

Data
t DM

Seen by slave
tAS

Address and
command

Data
tDS

t0 t1 t2

64

Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
Multiple-Cycle Transfers
Time

1 2 3 4

Clock

Address

Command

Data

Slave-ready

Figure 4.25. An input transfer using multiple clock cycles. 65

Asynchronous Bus – Handshaking
Protocol for Input Operation
Time

Address
and command

Master-ready

Slave-ready

Data

t0 t1 t2 t3 t4 t5

Bus cycle

Figure 4.26. Handshake control of data transfer during an input operation.

66
Asynchronous Bus – Handshaking
Protocol for Output Operation
Time

Address
and command

Data

Master-ready

Slave-ready

t0 t1 t2 t3 t4 t5

Bus cycle

Figure 4.27. Handshake control of data transfer during an output operation. 67

Discussion
 Trade-offs
 Simplicity of the device interface
 Ability to accommodate device interfaces that introduce
different amounts of delay
 Total time required for a bus transfer
 Ability to detect errors resulting from addressing a
nonexistent device or from an interface malfunction
 Asynchronous bus is simpler to design.
 Synchronous bus is faster.

68
Interface Circuits

69
Function of I/O Interface
 Provide a storage buffer for at least one word of
data;
 Contain status flags that can be accessed by the
processor to determine whether the buffer is full or
empty;
 Contain address-decoding circuitry to determine
when it is being addressed by the processor;
 Generate the appropriate timing signals required by
the bus control scheme;
 Perform any format conversion that may be
necessary to transfer data between the bus and the
I/O device.
70
Parallel Port
A parallel port transfers data in the form of a
number of bits, typically 8 or 16,
simultaneously to or from the device.
 For faster communications

71
Parallel Port – Input Interface (Keyboard
to Processor Connection)
Data

Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

Figure 4.28. Keyboard to processor connection.

72
 DATAIN

D7 Q7 D7

Keyboard
data

D0 Q0 D0

SIN
Status Valid
flag
Slave-
ready 1

Read-
status
Read-
data

R/ W
Master-
ready

A31
Address
decoder
A1

A0

Figure 4.29. Input interface circuit. 73

Parallel Port – Input Interface (Keyboard
to Processor Connection)

74
Parallel Port – Output Interface
(Printer to Processor Connection)

Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-eady
Output Idle
Slave-ready interface

Figure 4.31. Printer to processor connection. 75

76
 Bus
D7 PA7

DATAIN
D1
D0 PA0

SIN
Input
status CA

PB7

DATAOUT

PB0
SOUT
Handshake CB1
control CB2
Slave-
Ready 1

Master-
Ready
R/ W

A31
Address My-address
decoder
A2

RS1
A1

RS0
A0
77

Figure 4.33. Combined input/output interface circuit.

 D7 P7

DATAIN

D0 P0

DATAOUT

Data
Direction
Register

My-address
RS2
RS1 Status C1
Register
RS0 and
select control
R /W C2
Ready
Accept

INTR

78
Figure 4.34. A general 8-bit parallel interface.
Recall the Timing Protocol
Time

1 2 3 4

Clock

Address

Command

Data

Slave-ready

Figure 4.25. An input transfer using multiple clock cycles.

79
 DATAOUT

D7 D7 Q7
Printer
data
D0 D1 Q1
D0 D0 Q0

SOUT
Handshake Idle
control Valid
Read Load
status data

R/W
Slav e-
ready
Go
A31
Address My-address Timing
decoder Logic
A1

A0
Clock

My-address

Idle Respond
Go=1

80
Figure 4.35. A parallel point interface for the bus of Figure 4.25,
with a state-diagram for the timing logic.
Serial Port
A serial port is used to connect the processor
to I/O devices that require transmission of
data one bit at a time.
 The key feature of an interface circuit for a
serial port is that it is capable of
communicating in bit-serial fashion on the
device side and in a bit-parallel fashion on
the bus side.
 Capable of longer distance communication
than parallel transmission.
81
 Serial
Input shift register input

DATAIN

D7

D0

DATAOUT
My-address
RS1
RS0 Chip and
register Serial
R /W Output shift register output
select
Ready
Accept

Receiving clock
Status
I NTR and
control
Transmission clock

82
Figure 4.37. A serial interface.
Standard I/O
Interfaces

83
Overview
 The needs for standardized interface signals
and protocols.
 Motherboard

 Bridge: circuit to connect two buses

 Expansion bus

 ISA, PCI, SCSI, USB,…

84
 Main
Processor
memory

Processor bus

Bridge

PCI bus

Additional SCSI Ethernet USB ISA

memory controller interf ace controller interf ace

SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM K eyboard Game

Figure 4.38. An example of a computer system using different interface standards.

85