Computer Organization

21IST34
Module 4

Prepared by
MOHAN D N
Assistant Professor
Department of ISE ,NCET
Bengaluru
Accessing I/O Devices
Accessing I/O devices
Processor Memory

Bu
s

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the

memory via a bus.
•Bus consists of three sets of lines to carry address, data and control
signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the
address lines.
Accessing I/O devices (contd..)
I/O devices and the memory may
share the same address space:
⚫ Memory-mapped I/O.
⚫ Any machine instruction that can access memory can be used to
transfer
data to or from an I/O device.
⚫ Simpler software.

I/O devices and the memory may have

different address spaces:
⚫ Special instructions to transfer data to and from I/O devices.
⚫ I/O devices may have to deal with fewer address lines.
⚫ I/O address lines need not be physically separate from memory
address
lines.
⚫ In fact, address lines may be shared between I/O devices and
memory, with 20
a control signal5 to indicate whether it is a memory address or an
Accessing I/O devices (contd..)
Address
Bu lines
Data lines
s Control
lines

Addres Contr Data and I/O

s ol status interfa
decode circuit registers ce
r s

Input device

•I/O device is connected to the bus using an I/O interface circuit which
has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines
thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the
processor.
•Status register holds information necessary for the operation of the
Accessing I/O devices (contd..)
Recall that the rate of transfer to and from
I/O devices is slower than the speed of the
processor. This creates the need for
mechanisms to synchronize data transfers
between them.
Program-controlled I/O:
⚫ Processor repeatedly monitors a status flag to achieve the necessary
synchronization.
⚫ Processor polls the I/O device.

Two other mechanisms used for

synchronizing data transfers between the
processor and memory:
⚫ Interrupts.
⚫ Direct Memory Access.
Interrupts
Interrupts
 In program-controlled I/O, when the
processor continuously monitors the
status of the device, it does not
perform any useful tasks.
 An alternate approach would be for

the I/O device to alert the processor

when it becomes ready.
 Do so by sending a hardware signal called an interrupt to
the processor.
 At least one of the bus control lines, called an interrupt-
request line is
dedicated for this purpose.
 Processor can perform other useful
 Interrupts (contd..)
Program 1 Interrupt Service
routine

Interru
pt i
occur
s i+
here 1

•Processor is executing the instruction located at address i when an

interrupt occurs.
•Routine executed in response to an interrupt request is called the
interrupt-service routine.
•When an interrupt occurs, control must be transferred to the
interrupt service routine.
•But before transferring control, the current contents of the PC
(i+1), must be saved in a
known
Interrupts (contd..)
Treatment of an interrupt-service
routine is very similar to that of a
subroutine.
However there are significant
differences:
⚫ A subroutine performs a task that is required by the
calling
program.
⚫ Interrupt-service routine may not have anything in
common with
the program it interrupts.
⚫ Interrupt-service routine and the program that it
interrupts may
belong to different users.
⚫ As a result, before branching to the interrupt-service
routine, not only the PC, but other information such as
Interrupts (contd..)
• Saving and restoring information can be done
automatically by the processor or explicitly by
program instructions.
• Saving and restoring registers involves memory
transfers:
⚫ Increases the total execution time.
⚫ Increases the delay between the time an interrupt request is received, and
the start of execution of the interrupt-service routine. This delay is called
interrupt latency.
• In order to reduce the interrupt latency, most
processors save only the minimal amount of
information:
⚫ This minimal amount of information includes Program Counter and
processor status registers.
• Any additional information that must be saved, must
be saved explicitly by the program instructions at
the beginning of the interrupt service routine.
Interrupts (contd..)
 When a processor receives an
interrupt- request, it must branch
to the interrupt service routine.
 It must also inform the device that

it has recognized the interrupt

request.
 This can be accomplished in two

ways:
 Some processors have an explicit interrupt-
acknowledge control signal
for this purpose.
 In other cases, the data transfer that takes place
 Enabling and disabling
Interrupts
• Interrupt-requests interrupt the execution of
a program, and may alter the intended
sequence of events:
⚫ Sometimes such alterations may be undesirable, and must not be
allowed.
⚫ For example, the processor may not want to be interrupted by the same
device
while executing its interrupt-service routine.
• Processors generally provide the ability to
enable and disable such interruptions as
desired.
• One simple way is to provide machine
instructions such as Interrupt-enable and
Interrupt- disable for this purpose.
• To avoid interruption by the same device
during the execution of an interrupt
service routine:
Interrupts (contd..)
Multiple I/O devices may be connected
to the processor and the memory via a
bus. Some or all of these devices may
be capable of generating interrupt
requests.
⚫ Each device operates independently, and hence no definite
order can
be imposed on how the devices generate interrupt requests?

How does the processor know which

device has generated an interrupt?
How does the processor know which
interrupt service routine needs to be
executed?
When the processor is executing an
Interrupts (contd..)
Consider a simple arrangement where
all devices send their interrupt-
requests over a single control line in
the bus.
When the processor receives an interrupt
request over this control line, how does
it know which device is requesting an
interrupt?
This information is available in the status
register of the device requesting an
interrupt:
⚫ The status register of each device has an IRQ bit which it sets to 1
when it
requests an interrupt.
Interrupt service routine can poll the I/O
Interrupts (contd..)
 Thedevice requesting an interrupt
may identify itself directly to the
processor.
 Device can do so by sending a special code (4 to 8
bits) the processor
over the bus.
 Code supplied by the device may represent a part of the
starting address of the interrupt-service routine.
 The remainder of the starting address is obtained by the
processor based on other information such as the range of
memory addresses where interrupt service routines are
located.
 Usuallythe location pointed to by
the interrupting device is used to
Interrupts (contd..)
Previously, before the processor started
executing the interrupt service routine for
a device, it disabled the interrupts from
the device.
In general, same arrangement is used
when multiple devices can send
interrupt requests to the processor.
⚫ During the execution of an interrupt service routine of device,
the processor
does not accept interrupt requests from any other device.
⚫ Since the interrupt service routines are usually short, the delay
that this
causes is generally acceptable.

However, for certain devices this delay

may not be acceptable.
Interrupts (contd..)
 I/Odevices are organized in a
priority structure:
 An interrupt request from a high-priority device is accepted
while the processor is executing the interrupt service
routine of a low priority device.
A priority level is assigned to a
processor that can be changed under
program control.
 Priority level of a processor is the priority of the program that
is currently
being executed.
 When the processor starts executing the interrupt service
routine of a
device, its priority is raised to that of the device.
Interrupts (contd..)
 Processor’s priority is encoded in a
few bits of the processor status
register.
 Priority can be changed by instructions that write into the
processor
status register.
 Usually, these are privileged instructions, or instructions
that can be executed only in the supervisor mode.
 Privileged instructions cannot be executed in the user
mode.
 Prevents a user program from accidentally or intentionally
changing the
priority of the processor.
 If there is an attempt to execute a
Interrupts (contd..)
INTR1 I

Processo
NTRp
Device Device Device
1 2 p

r
INTA INTA p
1

Priority arbitration

•Each device has a separate interrupt-request and interrupt-

acknowledge line.
•Each interrupt-request line is assigned a different priority level.
•Interrupt requests received over these lines are sent to a priority
arbitration circuit
in the processor.
•If the interrupt request has a higher priority level than the priority
of the processor, then the request is accepted.
Interrupts (contd..)
Which interrupt request does the
processor accept if it receives
interrupt requests from two or more
devices simultaneously?.
If the I/O devices are organized in a
priority structure, the processor
accepts the interrupt request from a
device with higher priority.
⚫ Each device has its own interrupt request and interrupt
acknowledge line.
⚫ A different priority level is assigned to the interrupt request
line of each
device.
Interrupts (contd..)
Polling scheme:
•If the processor uses a polling mechanism to poll the status
registers of I/O devices to determine which device is requesting an
interrupt.
•In this case the priority is determined by the order in which the
devices are polled.
•The first device with status bit set to 1 is the device whose interrupt
request is I
accepted. Processo
NTR

Daisy chain scheme: Device 1

r
Device 2 Device n
INTA

•Devices are connected to form a daisy chain.

•Devices share the interrupt-request line, and interrupt-acknowledge
line is connected
to form a daisy chain.
•When devices raise an interrupt request, the interrupt-request line is
activated.
•The processor in response activates interrupt-acknowledge.
•Received by device 1, if device 1 does not need service, it passes the
signal to device 2.
Interrupts (contd..)
•When I/O devices were organized into a priority structure, each
device had its own interrupt-request and interrupt-acknowledge
line.
•When I/O devices were organized in a daisy chain fashion, the
devices shared an
interrupt-request line, and the interrupt-acknowledge propagated
through the devices.
•A combination of priority structure
Devic
and daisy chain
Devic
scheme can also
Processo
INTA
used. 1
e e

I NTR1
INTR
r
p

Device Device
INTA
Priority p
arbitration
circuit
•Devices are
organized into
groups.
•Each group is
assigned a different
Interrupts (contd..)
Only those devices that are being used in
a program should be allowed to generate
interrupt requests.
To control which devices are allowed to
generate interrupt requests, the interface
circuit of each I/O device has an interrupt-
enable bit.
⚫ If the interrupt-enable bit in the device interface is set to 1, then
the device is
allowed to generate an interrupt-request.
Interrupt-enable bit in the device’s
interface circuit determines whether the
device is allowed to generate an
interrupt request.
Interrupt-enable bit in the processor
Exceptions
Interrupts caused by interrupt-requests
sent by I/O devices.
Interrupts could be used in many other
situations where the execution of one
program needs to be suspended and
execution of another program needs to be
started.
In general, the term exception is used to
refer to any event that causes an
interruption.
⚫ Interrupt-requests from I/O devices is one type of an exception.

Other types of exceptions are:

⚫
Exceptions (contd..)
Many sources of errors in a
processor. For example:
⚫ Error in the data stored.
⚫ Error during the execution of an instruction.

When such errors are detected,

exception processing is initiated.
⚫ Processor takes the same steps as in the case of I/O
interrupt-
request.
⚫ It suspends the execution of the current program, and
starts
executing an exception-service routine.

Difference between handling I/O

interrupt- request and handling
exceptions due to errors:
Exceptions (contd..)
 Debugger uses exceptions to
provide important features:
 Trace,
 Breakpoints.
 Trace mode:
 Exception occurs after the execution of every
instruction.
 Debugging program is used as the exception-
service routine.
 Breakpoints:
 Exception occurs only at specific points selected by
the user.
 Debugging program is used as the exception-
service routine.
Exceptions (contd..)
 Certain instructions can be
executed only when the processor
is in the supervisor mode. These
are called privileged instructions.
 If an attempt is made to execute a

privileged instruction in the user

mode, a privilege exception occurs.
 Privilege exception causes:
 Processor to switch to the supervisor mode,
 Execution of an appropriate exception-servicing routine.
Direct Memory Access
Direct Memory Access (contd..)

Direct Memory Access (DMA):

⚫ A special control unit may be provided to transfer a block of
data directly between an I/O device and the main memory,
without continuous intervention by the processor.

Control unit which performs these

transfers is a part of the I/O device’s
interface circuit. This control unit is
called as a DMA controller.
DMA controller performs functions that
would be normally carried out by the
processor:
⚫ For each word, it provides the memory address and all the
control
signals.
Direct Memory Access (contd..)
DMA controller can transfer a block of
data from an external device to the
processor, without any intervention from
the processor.
⚫ However, the operation of the DMA controller must be under the
control of a
program executed by the processor. That is, the processor must
initiate the
DMA transfer.

To initiate the DMA transfer, the

processor informs the DMA
controller of:
⚫ Starting address,
⚫ Number of words in the block.
⚫ Direction of transfer (I/O device to the memory, or
Direct Memory Access
Main
Processor memory

System
bus

Disk/DMA DMA
Printer Keyboard
controller controller

Disk Disk Networ

k
Interfac
e

•DMA controller connects a high-speed network to the computer

bus.
•Disk controller, which controls two disks also has DMA capability. It
provides two DMA channels.
•It can perform two independent DMA operations, as if each disk
has its own DMA controller. The registers to store the memory
address, word count and status and control information are
duplicated.
Direct Memory Access (contd..)
Processor and DMA controllers have to
use the bus in an interwoven fashion to
access the memory.
⚫ DMA devices are given higher priority than the processor to
access the bus.
⚫ Among different DMA devices, high priority is given to high-
speed peripherals
such as a disk or a graphics display device.

Processor originates most memory

access cycles on the bus.
⚫ DMA controller can be said to “steal” memory access
cycles from the bus.
This interweaving technique is called as “cycle stealing”.

An alternate approach is the provide a

Bus arbitration
Processor and DMA controllers both
need to initiate data transfers on the
bus and access main memory.
The device that is allowed to initiate
transfers on the bus at any given time is
called the bus master.
When the current bus master
relinquishes its status as the bus
master, another device can acquire
this status.
⚫ The process by which the next device to become the bus
master is selected
and bus mastership is transferred to it is called bus
arbitration.
Centralized Bus Arbitration

B BS Y

BR

Processo
r

DMA DMA
controll controll
BG er BG er
1 1 2 2
Centralized Bus Arbitration(cont.,)
Bus arbiter may be the processor or a separate unit
connected to the bus.
Normally, the processor is the bus master, unless it
grants bus membership to one of the DMA
controllers.
DMA controller requests the control of the bus by
asserting the Bus Request (BR) line.
In response, the processor activates the Bus-Grant1
(BG1) line, indicating that the controller may use the
bus when it is free.
BG1 signal is connected to all DMA controllers in a
daisy chain fashion.
BBSY signal is 0, it indicates that the bus is busy.
Centralized arbitration (contd..)
DMA controller 2
asserts the BR Tim
signal. Processor
e
BR
asserts
the BG1 signal
BG1 BG1 signal
propagates
BG2 to DMA#2.

B BSY

Bus
mast
er Processo DMA controller Processo
r 2 r

Processor relinquishes
control
of the bus by setting BBSY
to 1.
Distributed arbitration
All devices waiting to use the bus
share the responsibility of carrying
out the arbitration process.
⚫ Arbitration process does not depend on a central arbiter
and hence
distributed arbitration has higher reliability.
Each device is assigned a 4-bit ID
number.
All the devices are connected using 5
lines, 4 arbitration lines to transmit the
ID, and one line for the Start-Arbitration
signal.
To request the bus a device:
⚫ Asserts the Start-Arbitration signal.
⚫ Places its 4-bit ID number on the arbitration lines.
Distributed arbitration
Distributed arbitration(Contd.,)
 Arbitration process:
 Each device compares the pattern that appears
on the arbitration lines to its own ID, starting with
MSB.
 If it detects a difference, it transmits 0’s on the
arbitration lines for that and all lower bit positions.
 The pattern that appears on the arbitration lines is
the logical-OR of all the 4-bit device IDs placed on
the arbitration lines.
Distributed arbitration (contd..)
•Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration lines.
•Device B has the ID 6 and wants to request the bus:
- Transmits the pattern 0110 on the arbitration lines.
•Pattern that appears on the arbitration lines is the logical OR of the
patterns:
- Pattern 0111 appears on the arbitration lines.

Arbitration process:
•Each device compares the pattern that appears on the arbitration
lines to its own
ID, starting with MSB.
•If it detects a difference, it transmits 0s on the arbitration lines for
that and all lower bit positions.
•Device A compares its ID 5 with a pattern 0101 to pattern 0111.
•It detects a difference at bit position 0, as a result, it transmits a
pattern 0100 on the
arbitration lines.
•The pattern that appears on the arbitration lines is the logical-OR of
0100 and 0110, which is 0110.
•This pattern is the same as the device ID of B, and hence B has won
Buses
Buses
 Processor, main memory, and I/O
devices are interconnected by
means of a bus.
 Bus provides a communication path

for the transfer of data.

 Bus also includes lines to support interrupts and
arbitration.
A bus protocol is the set of rules that
govern the behavior of various
devices connected to the bus, as to
when to place information on the bus,
Buses (contd..)
Bus lines may be grouped into three types:
⚫ Data
⚫ Address
⚫ Control

Control signals specify:

⚫ Whether it is a read or a write operation.
⚫ Required size of the data, when several operand sizes (byte, word,
long
word) are possible.
⚫ Timing information to indicate when the processor and I/O devices
may place
data or receive data from the bus.

Schemes for timing of data transfers over

a bus can be classified into:
⚫ Synchronous,
⚫ Asynchronous.
Synchronous bus

Bus clock

Bus cycle
Synchronous bus (contd..)
Tim
e
Bus
clock

Address
and
comman
d

Dat
a

t0 t1 t2

Bus
Master places the cycle
device address Addressed slave
and command on places Master “strobes” the
the bus, and data on the data data on the data lines
indicates that lines into its input buffer,
it is a Read for a Read operation.
• operation.
In case of a Write operation, the master places the data on the bus
along with the
address and commands at time t0.
•The slave strobes the data into its input buffer at time t2.
Synchronous bus (contd..)
 Once the master places the device
address and command on the bus, it
takes time for this information to
propagate to the devices:
 This time depends on the physical and electrical
characteristics of the
bus.
 Also, all the devices have to be given
enough time to decode the address
and control signals, so that the
addressed slave can place data on the
bus.
Synchronous bus (contd..)
 At the end of the clock cycle, at time t2,
the master strobes the data on the
data lines into its input buffer if it’s a
Read operation.
 “Strobe” means to capture the values of the data and store
them into a
buffer.
 When data are to be loaded into a
storage buffer register, the data
should be available for a period longer
than the setup time of the device.

Synchronous bus (contd..)
Time
Address & Bus
command clock Data reaches
appear on Seen the master.
tAM
the bus. by
master
Address
and
Dat
comman
Address & d a tDM
command
Seen by
reach the tAS
slave
slave. Address Data
and appears
on the bus.
command

Dat
a
tDS

t t 2
•Signals do not appear on
0
the bus as soon as they are placed on the bus,
1

t
due to the
propagation delay in the interface circuits.
•Signals reach the devices after a propagation delay which depends on
the
characteristics of the bus.
•Data must remain on the bus for some time after t equal to the hold
Synchronous bus (contd..)
 Data transfer has to be completed
within one clock cycle.
 Clock period t2 - t0 must be such that the longest propagation
delay on
the bus and the slowest device interface must be
accommodated.
 Forces all the devices to operate at the speed of the slowest
device.
 Processor just assumes that the data
are available at t2 in case of a Read
operation, or are read by the device in
case of a Write operation.
 What if the device is actually failed, and never really
Synchronous bus (contd..)
 Most buses have control signals to
represent a response from the slave.
 Control signals serve two purposes:
 Inform the master that the slave has recognized the address,
and is
ready to participate in a data transfer operation.
 Enable to adjust the duration of the data transfer operation
based on the
speed of the participating slaves.
 High-frequency bus clock is used:
 Data transfer spans several clock cycles instead of just one
clock cycle
as in the earlier case.
Synchronous bus (contd..)
Address & Tim
command e
requesting a Read 1 2 3 4
operation appear
on the bus.
Cloc
k

Addres
s

Comman
d Master strobes data
into the input buffer.
Dat
a

Slave-
ready

Slave places the data on the Clock changes are seen by all the
bus,
and asserts Slave-ready signal. devices
at the same time.
Asynchronous bus
Data transfers on the bus is controlled
by a handshake between the master
and the slave.
Common clock in the synchronous bus
case is replaced by two timing control
lines:
⚫ Master-ready,
⚫ Slave-ready.

Master-ready signal is asserted by the

master to indicate to the slave that it is
ready to participate in a data transfer.
Slave-ready signal is asserted by the
slave in response to the master-ready
Asynchronous bus (contd..)
 Datatransfer using the handshake
protocol:
 Master places the address and command information on the
bus.
 Asserts the Master-ready signal to indicate to the slaves that
the
address and command information has been placed on the
bus.
 All devices on the bus decode the address.
 Address slave performs the required operation, and
informs the processor it has done so by asserting the
Slave-ready signal.
 Master removes all the signals from the bus, once
Slave-ready is
asserted.
 If the operation is a Read operation, Master also
 Asynchronous bus (contd..) Tim
Address e
and
command

Master-
ready

Slave-
ready
Dat
a

t0 t1 t2 t3 t4 t5

Bus cycle
t0 - Master places the address and command information on the bus.
t1 - Master asserts the Master-ready signal. Master-ready signal is asserted
at t1 instead of t0
t2 - Addressed slave places the data on the bus and asserts the Slave-ready
signal.
t3 - Slave-ready signal arrives at the master.
t4 - Master removes the address and command information.
Asynchronous vs. Synchronous bus

 Advantages of asynchronous bus:

 Eliminates the need for synchronization between the sender
and the
receiver.
 Can accommodate varying delays automatically, using the
Slave-ready
signal.
 Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is limited by two-round
trip delays.
 Data transfers using a synchronous bus involves only one
round trip
delay, and hence a synchronous bus can achieve faster rates.
Interface Circuits
Interface circuits
I/O interface consists of the circuitry
required to connect an I/O device to a
computer bus.
Side of the interface which connects
to the computer has bus signals for:
⚫ Address,
⚫ Data
⚫ Control
Side of the interface which connects to
the I/O device has:
⚫ Data path and associated controls to transfer data between the
interface and
the I/O device.
⚫ This side is called as a “port”.
Ports can be classified into two:
⚫ Parallel port,
⚫ Serial port.
Interface circuits (contd..)
 Parallel port transfers data in the
form of a number of bits, normally 8
or 16 to or from the device.
 Serial port transfers and receives data

one bit at a time.

 Processor communicates with the bus

in the same way, whether it is a

parallel port or a serial port.
 Conversion from the parallel to serial and vice versa takes
place inside
the interface circuit.
Parallel port
Dat
a
Addres
DATAIN Dat
s
a Encoder
R/ and Keyboar
Processor W SIN
debounci d
Maste- ng circuit switche
rready Vali
Input d s
Slave-
ready interface

•Keyboard is connected to a processor using a parallel port.

•Processor is 32-bits and uses memory-mapped I/O and the
asynchronous bus
protocol.
•On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
Parallel port (contd..)
Dat
a
Addres
DATAIN Dat
s
a Encoder
R/ and Keyboar
Processor W SIN
debounci d
Maste- ng circuit switche
rready Vali
Input d s
Slave-
ready interfa
ce

•On the keyboard side of the interface:

- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce
(a single key
stroke may appear as multiple events to a processor).
- Data lines contain the code for the key.
- Valid line changes from 0 to 1 when the key is pressed. This
causes the code to be loaded into DATAIN and SIN to be set to
1.
Input Interface Circuit
•Output lines of DATAIN are
are connected to the data
lines of
the bus by means of 3 state
drivers
•Drivers are turned on when
the processor issues a read
signal and the address
selects this register.

•SIN signal is generated using a status

flag circuit.
•It is connected to line D0 of the processor
bus
using a three-state driver.
•Address decoder selects the input
interface based on bits A1 through A31.
•Bit A0 determines whether the status
or data register is to be read, when
Master-ready is active.
•
Parallel port (contd..)
Data

Address Dat
DATAOUT
a

Processor R/W
CPU SOUT Vali Printer
Master- d
ready Output Idl
e
Slave-
ready interfa
ce
•Printer is connected to a processor using a parallel port.
•Processor is 32 bits, uses memory-mapped I/O and asynchronous
bus protocol.
•On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
Parallel port (contd..)
Dat
a
Addres DATAOUT Dat
s a

CPU R/
Processor SOUT Vali Printer
W
d
Master-
ready Output Idl
Slave- e
ready interfa
ce
•On the printer side:
- Idle signal line which the printer asserts when it is ready to
accept a character.
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a
new character
on the data lines.
Circuit
•Data lines of the
processor bus are
connected to the
DATAOUT register of the
interface.
•The status flag SOUT is
connected to the data line D1
using a three-state driver.
•The three-state driver is
turned on, when the control
Read-status line is 1.
•Address decoder selects the
output interface using
address lines A1 through
A31.
•Address line A0 determines
whether the data is to be
loaded into the DATAOUT
register or status flag is to
be read.
•If the Load-data line is 1,
 Bus
D PA
7 7
DATAI
D N
1 PA
D
0 SIN
0 •Combined I/O interface
Input
statu CA circuit.
s
30
• bits arebits
Address used
A2to select the
through A31,
PB7
overall
that is
DATAOU
T interface.
•Address
PB0 bits selectbits
oneA1
of through
the threeA0,
SOUT
Handsha
that is, 2
CB1 namely,
registers, DATAIN, DATAOUT,
ekcontrol CB2 the status register.
and
Slave-
Read
y
1
•Status register contains the flags
SIN and
SOUT in bits 0 and 1.
Master- •Data lines PA0 through PA7
Read
y connect the
R/ W
A3 input device to the DATAIN
1 Addres
s
My-
address register.
decode
A2
r •DATAOUT register connects the
A1
RS1
data lines on the processor bus
RS0
to lines PB0 through PB7 which
A0 connect to the output device.
•Separate input and output data
lines for
 D P7
7 •Data lines to I/O device are
DATAIN bidirectional.
D P0
•both
Datainput, andthrough P0 can be
lines P7
0 •used forsome lines can be used for
In fact,
output.
input & some for output
depending on the pattern in the
DATAOUT •Data Direction
Processor Register
places (DDR).
an 8-bit pattern
•into
If a agiven
DDRbit position in the DDR
is 1, the corresponding data line
acts as an output line, otherwise
Data
it acts as an input line.
Directio •C1 and C2 control the interaction
n
Register between the interface circuit and
the I/O devices.
•are
Ready
connected
and Accept
to Master-ready
lines are &the
My-
address • Input
Slave-ready
handshake
signal My-address is
C1
RS2
Registe Statu control lines
connected on the
to the processor
output of an bus
r s and
RS1 side, and
address decoder.
select contr •Three register select lines that
RS0 ol
R/W allow up to 8
INTR C2 registers to be selected.
Ready

Accep
t
Serial port
 Serial port is used to connect the
processor to I/O devices that require
transmission of data one bit at a
time.
 Serial port communicates in a bit-

serial fashion on the device side

and bit parallel fashion on the bus
side.
 Transformation between the parallel and serial formats is
achieved with
shift registers that have parallel access capability.
 Input shift register Seria
l
inpu
t •Input shift register accepts input
one
at a bit
time from the I/O device.
DATAI •Once all the 8 bits are
N
received, the
loaded
contents inof
parallel
the input
intoshift
DATAIN
register.
register are
•Output data in the DATAOUT
D register are loaded into the
7
output
registershift
and register.
sent out to the I/O
D •
bit
Bits
at are
device aonshifted out of the
0
•
time.
output
As soonshift
as data from the input
My- DATAOUT shift
are reg. into DATAIN, it can
loaded
address
RS1 start
RS0 •
accepting
Input shift
another
register8 and
bits of
DATAIN
Chip
Serialare
data.
register
both used at input so that the
R /W and Output shift register
Ready
selec
register input shift register can start
t
receiving another set of 8 bits
Accep from the input device after
Receiving
t
Statu clock loading the contents to DATAIN,
I
NTR
s and
ransmission before the
DATAIN. processor
This is calledreads
as the
contr
ol
clock contents of
double-
T
buffering.
Serial port (contd..)
Serial interfaces require fewer wires, and
hence serial transmission is convenient
for connecting devices that are physically
distant from the computer.
Speed of transmission of the data over a
serial interface is known as the “bit
rate”.
⚫ Bit rate depends on the nature of the devices connected.

In order to accommodate devices with a

range of speeds, a serial interface must
be able to use a range of clock speeds.
Several standard serial interfaces have
been developed: