Computer Organization

Text book:
Computer Organization: C Hamacher, Z Vranesic, S
Zaky:, Tata McGraw Hill, 5th Edition, 2011.
 Module 3-Arithmetic Unit

Topics:
• Arithmetic unit: Multiplication of Positive
numbers, A signed operand multiplication
• Bit pair recoding of multipliers, carry save
addition of summands
• Integer division – Restoring and Non-restoring
division
Unsigned binary number
• In some applications, all data is either positive or negative. When
this happens, you can forget about + and - signs, and concentrate
on the magnitude (absolute value) of numbers.
• For instance, the smallest 8-bit number is 0000 0000, and the
largest is 1111 1111. Therefore, the total range of 8-bit numbers is
0000 0000 (00H) to 1111 1111 (FFH)
• This is equivalent to a decimal 0 to 255. As you can see, + or – signs
are not included with these decimal numbers.
• With 16-bit numbers, the total range is 0000 0000 0000 0000
(0000H) to 1111 1111 1111 1111 (FFFFH)
which represents the magnitude of all decimal numbers from 0 to
65,535.
• Data of the foregoing type is called unsigned binary because all of
the bits in a binary number are used to represent the magnitude of
the corresponding decimal number.
Sign-magnitude number
• Since everything has to be coded as strings of 0s and ls, the+
and- signs also have to be represented in binary form.
• For reasons given soon, 0 is used for the + sign and 1 for the -
sign.
• Therefore, -001, -010, and-011 are coded as 1001, 1010, and
1011.
• The foregoing numbers contain a sign bit followed by magnitude
bits. Numbers in this form are called sign-magnitude numbers.
• In signed magnitude number (–) is represented by 1 and (+) as 0.
– +101=0101
– - 001=1001
• Range of sign magnitude number
– 0 to 255 becomes -127 to +127
Multiplication of Positive numbers
Multiplication of Positive numbers
Full Adder TT

A B C S C

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
 Multiplication of Positive numbers
• The product of two n-digit numbers can be accommodated in 2n digits, so
the product of the two 4-bit numbers in this example fits into 8 bits.
• If the multiplier bit is 1, the multiplicand is entered in the appropriate
position to be added to the partial product If the multiplier bit is 0, then 0s
are entered, as in the third row of the example.
• The main component in each cell is a full adder FA. The AND gate in each
cell determines whether a multiplicand bit, mj is added to the incoming
partial-product bit, based on the value of the multiplier bit, q;. Each row i,
where 0 <= i >= 3, adds the multiplicand (appropriately shifted) to the
incoming partial product, PPi, to generate the outgoing partial product,
PP(i + 1),if qj = 1.
• If qj = 0, PPi is passed vertically downward unchanged. PP0 is all 0s, and
PP4 is the desired product. The multiplicand is shifted left one position per
row by the diagonal signal path.
• The worst case signal propagation delay path is from the upper right
comer of the array to the high-order product bit output at the bottom
left comer of the array.
 Multiplication of Positive numbers
• The simplest way to perform multiplication is to use the adder
circuitry in the ALU for a number of sequential steps.
• The block diagram in Figure 6.7a shows the hardware arrangement for
sequential multiplication. This circuit performs multiplication by using a
single n-bit adder n times to implement the spatial addition performed by
the n rows of ripple-carry adders of Figure 6.6b. Registers A and Q
combined hold PPi while multiplier bit q; generates the signal Add/No add.
• This signal controls the addition of the multiplicand, M, to PPi to generate
PP(i + l). The product is computed in n cycles. The partial product grows
in length by one bit per cycle from the initial vector, PPO, of n 0s in
register A.
• The carry-out from the adder is stored in flip-flop C, shown at the left end
of register A. At the start, the multiplier is loaded into register Q, the
multiplicand into register M, and C and A are cleared to 0. At the end of
each cycle, C, A, and Q are shifted right one bit position to allow for
growth of the partial product as the multiplier is shifted out of register Q
Multiplication of Positive numbers
Multiplication of Positive numbers
 Multiplication of Positive numbers
• Because of this shifting, multiplier bit q; appears at the
LSB position of Q to generate the Add/Noadd signal at
the correct time, starting with q0 during the first cycle; q1
during the second cycle, and so on. After they are used,
the multiplier bits are discarded by the right-shift
operation.
• Note that the carry-out from the adder is the leftmost bit
of PP(i + 1), and it must be held in the C flip-flop to be
shifted right with the contents of A and Q.
• After n cycles, the high-order half of the product is held
in register A and the low-order half is in register Q. The
multiplication example of Figure 6.6a is shown in Figure
6.7b as it would be performed by this hardware
arrangement.
 Multiplication of Positive numbers

• Using this sequential hardware structure, it is clear

that a Multiply instruction takes much more time to
execute than an Add instruction.
Multiplication of Signed Numbers
The Booth Algorithm
• The Booth algorithm generated a 2n-bit product and
treats both positive and negative 2’s-complement n-bit
operands uniformly.
• The Booth Algorithm has two attractive features. First it
handles both positive and negative multipliers uniformly.
Second it achieves some efficiency in the number of
additions required when the multiplier has a few large
blocks of 1s.
The Booth algorithm applied for negative multiplier
 Fast Multiplication

We now describe two techniques for speeding up the

multiplication operation.
• The first technique (bit-pair recoding) guarantees
that the maximum number of summands (versions of
the multiplicand) that must be added is n/2 for n-bit
operands;
• The second technique reduces the time needed to
add the summands.
 1.Bit pair recoding of multipliers
• A technique called bit-pair recoding halves the maximum
number of summands. It is derived directly from the Booth
algorithm. Group the Booth-recoded multiplier bits in pairs
Example:

As [-1 0] = -1 x 2 1 + 0 x 2 0 = -2 + 0= -2
[ -1 +1] = -1 x 2 1 + 1 x 2 0 = -2 + 1= -1
[0 0] = 0 x 2 1 + 0 x 2 0 = 0 + 0= 0
 1.Bit pair recoding of multipliers
• Figure 6.14b shows a table of the multiplicand selection decisions
for all possibilities.
 1.Bit pair recoding of multipliers
• Example

1. Using Booth Algo 2. Using Bit- Pair

 2. Carry save addition of summands
1. Ripple –Carry Array
• Multiplication requires the addition of several
summands. A technique called carry­ save addition
(CSA) speeds up the addition process. Consider the
array for 4 x 4 multiplication shown in Figure 6.l6a.
• This structure is the general array shown in Figure
6.6, with the first row consisting of just the AND
gates that implement the bit products m3q0, m2q0,
m1q0, and m0q0.
• Disadvantage: Carries ripple along the rows
1. Ripple - Carry Array
2. carry save addition of summands
Generates S and C in parallel .
• Instead of letting the carries ripple along the rows.
• It can be "saved" and introduced into the next row, at the correct weighted
positions, as shown in Figure 6.16b. This frees up an input to three full
adders in the first row.
• These inputs are used to introduce the third summand bit products m2q2 ,
m 1q2, and m0qz. Now, two inputs of each full adder in the second row are
fed by sum and carry outputs from the first row. The third input is used to
introduce the bit products m2q3, m1q3, and moq3 of the fourth summand.
• The high-order bit products m3q2 and m3q3 of the third and fourth
summands are introduced into there remaining free inputs at the left end in
the second and third rows. The saved carry bits and the sum bits from the
second row are now added in the third row to produce the final product
bits.
2. carry save addition of summands

Advantage and steps:

• A more significant reduction in delay can be achieved as
follows. Consider the addition of many summands, as
required in the multiplication of longer operands. We can
group the summands in threes and perform carry-save
addition on each of these groups in parallel to generate a set
of S and C vectors in one full-adder delay.
• Next, we group all of the S and C vectors into threes, and
perform carry-save addition on them, generating a further set
of S and C vectors in one more full-adder delay. We continue
with this process until there are only two vectors remaining.
• They can then be added in a ripple-carry or a carry-
lookahead adder to produce the desired product.
Ex. 13X 11 1m3 1m2 0m1 1m0
1q3 0q2 1q1 1q0More significant reduction in delay as follow
---------------------
1m3q0 1m2q0 0m1q0 1m0q0 A S 1C 1
1m3q1 1m2q1 0m1q1 1m0q1 X B
0m3q2 0m2q2 0m1q2 0m0q2 X X C
1m3q3 1m2q3 0m1q3 1m0q3 X X X D
S 2C 2
1 0 0 0 1 1 1 1

Example 1 1 0 1
1 0 1 1
1 1 0 1 A
1 1 0 1 X B
0 0 0 0 x x C
0 1 0 1 1 1 S1
0 1 0 0 0 C1
1 1 0 1 x x x D
1 1 0 1 1 1 1 S2
0 1 0 0 0 0 C2 binary addition along with carry
1 0 0 0 1 1 1 1
2. carry save addition of summands
2. carry save addition of summands
• Example 45 [M] x 63 [Q] = 2835 Conventional Method
• More significant
reduction delay Using
Carry Save addition
• Using Carry addition- Schematic representation
 Integer Division

Two types:
1. Restoring Division
2. Non- Restoring Division
1. Restoring Division
• Figure 6.21 shows a logic circuit arrangement that implements restoring
division. Note its similarity to the structure for multiplication that was
shown in Figure 6.7. An n-bit positive divisor is loaded into register M and
an n-bit positive dividend is loaded into register Q at the start of the
operation.
• Register A is set to 0. After the division is complete, the n-bit quotient is in
register Q and the remainder is in register A. The required subtractions
are facilitated by using 2's-complement arithmetic. The extra bit position
at the left end of both A and M accommodates the sign bit during
subtractions.
 Integer Division
1. Restoring Division

Quotient

Dividend
Divisor
00

Remainder
 Integer Division
1. Restoring Division

Example-1 : Perform division of 8/3 using

Restoring Division Concept.
 Integer Division

2. Non-Restoring Division
• The restoring-division algorithm can be improved by avoiding
the need for restoring A after an unsuccessful subtraction.
Subtraction is said to be unsuccessful if the result is negative.
Consider the sequence of operations that takes place after the
subtraction operation in the preceding algorithm.
• If A is positive, we shift left and subtract M, that is, we perform
2A – M (A=A-M). If A is negative, we restore it by performing A
+ M, and then we shift it left and subtract M. This is equivalent
to performing 2A + M. (A=A+M).
• The q0 bit is appropriately set to 0 or 1 after the correct
operation has been performed. We can summarize this in the
following algorithm for nonrestoring division.
• Step 2 is needed to leave the proper positive
remainder in A at the end of the n cycles of Step 1.
• The logic circuitry in Figure 6.21 can also be used to
perform this algorithm. Note that the Restore
operations are no longer needed; and that exactly
one Add or Subtract operation is performed per cycle
 • Non-Restoring Division

Example-2 : Perform division of 8/3 using

Non-Restoring Division Concept.