1.CA Intro Class Lecture
1.CA Intro Class Lecture
Architecture
Introductory Class
Instructor
Dr. Fakir Sharif Hossain
Associate professor
Dept. of EEE, AUST, Dhaka
Course Objectives:
b. To understand the design of the various functional units and components of computers.
Course Contents:
Instructions and data access methods; Arithmetic Logic Unit (ALU) design: arithmetic and
logical operations, floating point operations; Process design: data paths single cycle and multi
cycle implementations; Control Unit Design: hardware and micro programmed Pipeline: pipeline
data path and control, hazards and exceptions; Memory Organization: cache, virtual memory,
buses, multiprocessor, type of microprocessor performance, single bus multiprocessors,
clusters.
Sl. COs Mapping of Course
POs(K CEP/ withBloom’s
Outcomes Assessment
Bloom’s Taxonomy and
No. ) EA(P/A) Taxonomy rubrics(Marks)
Programme Outcomes
1+Best 2 out
of 3 Quizes CT-2: Assignment, Topic: Pipeline 20
3 units:
1) Input unit
2) Central
Processing
Unit
3) Output unit
Computer
Top Level
Structure
(single core)
Simplified view
of Multicore
Computer
3) L3 cache: (2MB-256MB) {large size, low speed} [ between two separated core]
Difference between cache memory and cache
file
Cache memory is a hardware component built into the
CPU, while cache files are temporary data storage areas
on a computer's hard drive or SSD.
CSE-4293 Computer @ Hossain 11
computer Architecture
planning
Analog (mechanical)
Electromechanical (Digital)
Cite: https://en.wikipedia.org/wiki/Computer
cite: https://en.wikipedia.org/wiki/Microprocessor_chronol
ogy
Year: 1980-2020